MT9162 MITEL, MT9162 Datasheet - Page 4

• Manufacturer Part Number: MT9162
• Description: ISO2-CMOS 5 Volt Single Rail Codec
• Manufacturer: MITEL

MT9162
TxMute pin is high. When either of these pins are low
their respective paths function normally. The -Zero
entry of Table 1 is used for the quiet code definition.
SSI Mode
The SSI BUS consists of input and output serial data
streams named Din and Dout respectively, a Clock
input signal (CLOCKin), and a framing strobe input
(STB). A 4.096 MHz master clock is also required for
SSI operation if the bit clock is less than 512 kHz.
7-164
CSL
1
1
0
0
0
0
Serial
D
D
2
in
out
PCM
PCM
CSL
Port
Table 2: Bit Clock Rate Selection
0
0
0
0
1
1
1
-2.05 dB
CSL
Encoder
Decoder
2.05 dB
0
1
0
1
0
1
0
Rate (kHz)
Clock Bit
External
Transmit Filter
(1 dB steps)
Transmit Filter
1536
2048
4096
0 to +7 dB
128
256
512
Gain
0dB
Gain
Filter/Codec and Analog Interface
Figure 3 - Audio Gain Partitioning
CLOCKin
Internal To Device
(kHz)
Filter Gain
4096
4096
1536
2048
4096
Receive
512
0 dB
Transmit Gain
-0.37 dB
The timing requirements for SSI are shown in
Figures 5 & 6.
In SSI mode the MT9162 supports only B-Channel
operation. Hence, in SSI mode transmit and receive
B-Channel data are always in the channel defined by
the STB input.
The data strobe input STB determines the 8-bit
timeslot used by the device for both transmit and
receive data. This is an active high signal with an 8
kHz repetition rate.
SSI operation is separated into two categories based
upon the data rate of the available bit clock. If the bit
clock is 512 kHz or greater then it is used directly by
the internal MT9162 functions allowing synchronous
operation. If the available bit clock is 128 kHz or 256
kHz, then a 4096 kHz master clock is required to
derive clocks for the internal MT9162 functions.
Applications where Bit Clock (BCL) is below 512 kHz
are designated as asynchronous. The MT9162 will
re-align its internal clocks to allow operation when
the external master and bit clocks are asynchronous.
Control pins CSL2, CSL1 and CSL0 are used to
program the bit rates.
Transmit
8.42 dB
Gain
Receiver
-2.05 dB
Driver
Advance Information
Aout +
Aout-
AIN+
AIN-
External To Device
Analog
Input
20k