MT91L61 MITEL, MT91L61 Datasheet - Page 7

• Manufacturer Part Number: MT91L61
• Description: (MT91L60 / MT91L61) ISO2-CMOS 3 Volt Multi-Featured Codec
• Manufacturer: MITEL

Advance Information
When 0, D-Channel data is shifted at the rate of 2
bits/frame (16 kb/s default).
16 kb/s D-Channel operation is the default mode
which allows the microprocessor access to a full byte
of D-Channel information every fourth ST-BUS
DATA 2
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
DATA 1
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
subsequent byte is always data until terminated via CS returning high.
subsequent byte is always data until terminated via CS returning high.
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
Delays due to internal processor timing which are transparent .
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
Delays due to internal processor timing which are transparent.
The MT91L60/L61:latches received data on the rising edge of SCLK.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
The MT91L60/L61: latches received data on the rising edge of SCLK.
D
D
7
0
D
D
Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire
COMMAND/ADDRESS
6
COMMAND/ADDRESS
1
D
D
-outputs transmit data on the falling edge of SCLK.
5
2
-outputs transmit data on the falling edge of SCLK.
D
D
4
3
D
D
3
4
Figure 4 - Serial Port Relative Timing for Intel Mode 0
D
D
2
5
D
D
1
6
D
D
0
7
1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused
1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused
D
D
D
D
7
0
0
7
D
D
D
D
6
1
1
6
DATA INPUT/OUTPUT
DATA INPUT/OUTPUT
D
D
D
D
5
2
2
5
D
D
D
D
4
3
3
4
D
frame. By arbitrarily assigning ST-BUS frame n as
the
microprocessor D-Channel read and write operations
are performed, then:
D
D
D
3
4
3
4
D
D
D
D
2
5
2
5
reference
D
D
D
D
1
6
1
6
D
R/W
X
7
D
D
D
D
D
7
0
7
0
7
X
X
D
D
D
D
0
7
0
7
frame,
X
X
D
D
D
D
1
6
1
6
COMMAND/ADDRESS:
COMMAND/ADDRESS:
D
D
D
D
X
X
2
5
2
5
D
D
D
D
3
4
during
A
4
MT91L60/61
3
A
2
D
D
2
D
D
3
4
3
4
D
A
D
D
D
A
1
2
5
2
5
1
D
D
D
D
which
1
6
1
6
A
A
0
D
D
D
D
0
0
7
7
0
R/W
D
D
X
0
0
the
7