MT9V012 Micron, MT9V012 Datasheet - Page 24

• Manufacturer Part Number: MT9V012
• Description: 1/6-Inch VGA CMOS Digital Image Sensor
• Manufacturer: Micron

Table 6:
PDF: 814eb99f/Source: 8175e929
MT9V012_2.fm - Rev. B 2/05 EN
0x0A (10) Row Speed
0x0B (11) Extra Delay
0x0C (12) Shutter Delay
0x0D (13) Reset
15:14
13:0
10:0
Bit
7:4
13
2:
3
8
0
1
2
3
4
5
6
Pixel Clock
Speed
Reserved
Delay Pixel
Clock
Invert Pixel
Clock
Reserved
Reserved
Extra Delay
Shutter Delay
Reset
Restart
Standby
Reserved
Output Disable
Reserved
Drive outputs
Register Description (continued)
A programmed value of N gives a pixel clock period of (2 x N)
master clocks. A value of 0 is treated like (and reads back as)
a value of 1.
Read-only.
Number of half-master-clock-cycle increments to delay the
rising edge of PIXCLK relative to transitions on
FRAME_VALID, LINE_VALID, and D
Invert PIXCLK. When clear, FRAME_VALID, LINE_VALID, and
D
PIXCLK. When set, FRAME_VALID, LINE_VALID, and D
set up relative to the delayed falling edge of PIXCLK.
Reserved. Do not change from default value.
Reserved. Do not change from default value.
Extra blanking inserted between frames. A programmed
value of N increases the vertical blanking time by N pixel
clock periods. Can be used to get a more exact frame rate.
May affect the integration times of parts of the image when
the integration time is less than 1 frame.
The amount of time from the end of the sampling sequence
to the beginning of the pixel reset sequence. This register
should normally be set to zero. A non-zero value will only
have a visible effect on the image when the integration time
(Reg0x09) is small. A programmed value of N reduces the
integration time by N master clock periods (N / 2) pixel clock
periods). Legal values for this register are shown in
"Maximum Shutter Delay" on page 37.
Setting this bit puts the sensor into reset; the frame being
generated will be truncated, and the signal interface will go
to an idle state. All internal registers (except for this bit) will
go to the default power-up state. Clearing this bit resumes
normal operation.
Setting this bit causes the sensor to truncate the current
frame and start resetting the first row. The delay before the
first valid frame is read out equals the integration time. This
bit is write-1, but always reads back as “0.”
Setting this bit places the sensor in a low-power state. See
“Power Saving Modes” on page 42.
This read/write bit has no function.
Setting this bit puts the signal interface into High-Z. See
“Output Enable Control” on page 41.
Reserved.
By default, asserting STANDBY causes the signal interface to
enter High-Z. Setting this bit stops STANDBY from
contributing to output-enable control. See “Output Enable
Control” on page 41.
OUT
are set up relative to the delayed rising edge of
Bit Description
MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
24
OUT
.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
OUT
are
Default
(hex)
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
©2004 Micron Technology, Inc. All rights reserved.
to Frame
Sync’d
Start
N
N
N
N
N
N
N
N
N
Y
Y
Y
Preliminary
Registers
Frame
Bad
YM
YM
YM
YM
N
N
N
N
N
N
N
‡