MT8941 Mitel Networks Corporation, MT8941 Datasheet
MT8941
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MT8941 Summary of contents
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... Advanced T1/CEPT Digital Trunk PLL MT8941AE MT8941AP Description The MT8941 is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The ...
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... MT8941 CMOS 1 24 ENVC 2 23 MS0 22 C12i 3 21 MS1 F0i 19 F0b 6 18 MS2 7 17 C16i 8 ENC4o 16 9 C8Kb 15 10 C4o VSS 12 24 PIN PDIP Pin Description Pin # Name DIP PLCC Variable clock enable (TTL compatible input) - This input directly controls the three states (pin 22) under all modes of operation ...
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... RST Reset (Schmitt trigger input) - This input (active LOW) puts the MT8941 in its reset state. To guarantee proper operation, the device must be reset after power-up. The time constant for a power-up reset circuit (see Figures 9-13) must be a minimum of five times the rise time of the power supply ...
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... MT8941 CMOS Functional Description The MT8941 is a dual digital phase-locked loop providing the timing and synchronization signals to the interface circuits for T1 and CEPT (30+2) Primary Multiplex Digital Transmission links. As shown in the functional block diagram (see Figure 1), the MT8941 has two digital phase-locked loops (DPLLs), associated output controls and the mode selection logic circuits ...
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... MHz for DPLL #1 and 16.384 MHz for DPLL #2 over the entire temperature range of operation. The inputs MS0 to MS3 are used to select the operating mode of the MT8941, see Tables All the outputs are controlled to the high impedance condition by their respective enable controls. The uncommitted NAND gate is available for use in applications involving Mitel’ ...
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... MT8941 CMOS The operation of DPLL #2 in SINGLE CLOCK-1 mode is identical to SINGLE CLOCK-2 mode, providing the CEPT and ST-BUS compatible timing signals synchro-nized to the internal 8 kHz signal obtained from DPLL#1 in DIVIDE mode. SINGLE CLOCK-1 mode is selected for DPLL #2, it automatically selects the DIVIDE-1 mode for DPLL #1, and thus, an external 1 ...
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... The spectrum of the intrinsic jitter for both DPLLs of the MT8941 is shown in Figure 5. The typical peak-to-peak value for this jitter is 0.07UI. The transfer function, which is the ratio of ...
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... MT8941 CMOS Fig. 5- The Spectrum of the Inherent Jitter for either PLL Fig The Jitter Transfer Function for PLL1 Fig The Jitter Transfer Function for PLL2 3-50 ...
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... U MT8941 X Clocks 8 kHz Reference Signal Figure 8 - Application Differences between the MT8940 and MT8941 it is recommended to use a ±32 ppm oscillator for DPLL #2 and a ±100 ppm oscillator for DPLL #1. Differences between MT8941 and MT8940 The MT8941 and MT8940 are pin and mode compatible for most applications. However, the user should take note of the following differences between the two parts ...
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... The MT8941 must be reset after power-up in order to guarantee proper operation, which is not the case for the MT8940. 4. For the MT8941, DPLL #2 locks to the falling edge of the C8Kb reference signal. the MT8940 locks on to the rising edge of C8Kb. 5. While the MT8940 is available only pin plastic DIP, the MT8941 has an additional 28 pin PLCC package option ...
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... R DPLL #2 - FREE-RUN Synchronization and Timing Signals for the CEPT Transmission Link The MT8941 can be used to provide the timing and synchronization signals for the MH89790/790B, Mitel’s CEPT (30+2) Digital Trunk Interface Hybrid. Since the operational frequencies of the ST-BUS and the CEPT primary multiplex digital trunk are the same, only DPLL #2 is required ...
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... C2o V SS Figure 12 - Synchronization at the Slave End of the CEPT Digital Transmission Link Figures 11 and 12 show how the MT8941 can be used to synchronize the ST-BUS to the CEPT transmission link at the master and slave ends. Generation of ST-BUS Timing Signals The MT8941 can source the properly formatted ST- BUS timing and control signals with no external inputs except the crystal clock ...
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... IH V 3 1.0 1 -100 - 120 IL I -10 ±1 +10 IL MT8941 CMOS Min Max Units -0.3 7.0 V -0 ±10 ±25 ±50 -55 125 1200 600 ) unless otherwise stated. SS Units Test Conditions unless otherwise stated. Units Test Conditions mA ...
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... MT8941 CMOS AC Electrical Characteristics Characteristics 1 CVb output (1.544 MHz) rise time 2 CVb output (1.544 MHz) fall time D 3 CVb output (1.544 MHz) clock P period CVb output (1.544 MHz) clock width (HIGH CVb output (1.544 MHz) clock width (LOW delay (HIGH to LOW) ...
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... V OH C4o 42LH t 42HL V OH C2o W2oL V OH C2o V OL Figure 16 - Timing Information on DPLL #2 Outputs t t C8LL Figure 15 - DPLL #1 in DIVIDE Mode t WFP t FPH t fC4 t t 4oLH 4oHL t P2o t W2oH t fC2 t 2oLH MT8941 CMOS ICLH t P4o t rC4 t rC2 t 2oHL 3-57 ...
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... MT8941 CMOS AC Electrical Characteristics Characteristics 1 C4b output clock period 2 C4b output clock width (HIGH) 3 C4b output clock width (LOW) 4 C4b output clock rise time 5 C4b clock output fall time 6 Frame pulse output delay (HIGH to LOW) from C4b 7 Frame pulse output delay ...
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... WFP t 244 P4o WFP P4o MT8941 CMOS (Refer to Figure 14) ) unless otherwise stated. SS Units Test Conditions ns ns For DPLL #1, while operating to ns provide the T1 clock signal. For DPLL #2, while operating to ns provide the CEPT and ST-BUS timing signals. ...
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... MT8941 CMOS AC Electrical Characteristics Characteristics 1 Delay from Enable to Output (HIGH to THREE STATE Delay from Enable to Output U (LOW to THREE STATE Delay from Enable to Output U (THREE STATE to HIGH Delay from Enable to Output (THREE STATE to LOW) † Timing is over recommended temperature & power supply voltages. ...