MT8941 Mitel Networks Corporation, MT8941 Datasheet - Page 17

• Manufacturer Part Number: MT8941
• Description: CMOS ST-BUS FAMILY Advanced T1/CEPT Digital Trunk PLL
• Manufacturer: Mitel Networks Corporation

† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Please review the section on "Jitter Performance and Lock-in Range".
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics
AC Electrical Characteristics
1
2
3
4
5
6
Master clock
inputs
1
2
3
4
F0b
C4b
C
L
O
C
K
S
F0b input pulse width (LOW)
C4b input clock period
Frame pulse (F0b) setup time
Frame pulse (F0b) hold time
Master clocks input rise time
Master clocks input fall time
Master clock period
(12.352MHz)*
Master clock period
(16.384MHz)*
Duty Cycle of master clocks
Lock-in Range
V
V
V
V
IH
IL
IH
IL
Characteristics
Characteristics
2.4 V
1.5 V
0.4 V
Figure 18 - External Inputs on C4b and F0b for the DPLL #2
DPLL #1
DPLL #2
t
FS
t
r
† - Voltages are with respect to ground (V
† - Voltages are with respect to ground (V
Sym
t
t
Figure 17 - Master Clock Inputs
P12
P16
t
P12
t
t
Sym
t
r
f
t
WFP
t
t
P4o
FH
FS
or t
t
P16
WFP
80.943
61.023
-2.33
-1.69
Min
45
Min
t
FH
t
P4o
80.958
61.035
Typ
Typ
50
244
244
50
25
‡
‡
80.974
61.046
+2.33
+1.69
Max
Max
10
10
55
SS
SS
) unless otherwise stated.
) unless otherwise stated.
Units
Units
ns
ns
ns
ns
Hz
ns
ns
ns
ns
%
CMOS
For DPLL #1, while operating to
provide the T1 clock signal.
For DPLL #2, while operating to
provide the CEPT and ST-BUS
timing signals.
With the Master frequency
tolerance at ±32 ppm.
Test Conditions
t
Test Conditions
f
(Refer to Figure 14)
(Refer to Figure 18)
MT8941
3-59