SST89V58RD Silicon Storage Technology, SST89V58RD Datasheet - Page 42

• Manufacturer Part Number: SST89V58RD
• Description: FlashFlex51 MCU
• Manufacturer: Silicon Storage Technology

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Data Sheet
6.1.2 Automatic Address Recognition
Automatic Address Recognition helps to reduce the MCU
time and power required to talk to multiple serial devices.
Each device is hooked together sharing the same serial
link with its own address. In this configuration, a device is
only interrupted when it receives its own address, thus
eliminating the software overhead to compare addresses.
This same feature helps to save power because it can be
used in conjunction with idle mode to reduce the system’s
overall power consumption. Since there may be multiple
slaves hooked up serial to one master, only one slave
would have to be interrupted from idle mode to respond to
the master’s transmission. Automatic Address Recognition
(AAR) allows the other slaves to remain in idle mode while
only one is interrupted. By limiting the number of interrup-
tions, the total current draw on the system is reduced.
There are two ways to communicate with slaves: a group of
them at once, or all of them at once. To communicate with a
group of slaves, the master sends out an address called
the given address. To communicate with all the slaves, the
master sends out an address called the “broadcast”
address.
AAR can be configured as mode 2 or 3 (9-bit modes) and
setting the SM2 bit in SCON. Each slave has its own SM2
bit set waiting for an address byte (9th bit = 1). The Receive
Interrupt (RI) flag will only be set when the received byte
matches either the given address or the broadcast
address. Next, the slave then clears its SM2 bit to enable
reception of the data bytes (9th bit = 0) from the master.
When the 9th bit = 1, the master is sending an address.
When the 9th bit = 0, the master is sending actual data.
If mode 1 is used, the stop bit takes the place of the 9th bit.
Bit RI is set only when the received command frame
address matches the device’s address and is terminated
by a valid stop bit. Note that mode 0 cannot be used. Set-
ting SM2 bit in the SCON register in mode 0 will have no
effect.
Each slave’s individual address is specified by SFR
SADDR. SFR SADEN is a mask byte that defines “don’t
care” bits to form the given address when combined with
SADDR. See the example below:
©2006 Silicon Storage Technology, Inc.
Slave 1
SADDR =
SADEN =
GIVEN
= 1111 0X0X
1111 0001
1111 1010
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
42
6.1.2.1 Using the Given Address to Select Slaves
Any bits masked off by a 0 from SADEN become a “don’t
care” bit for the given address. Any bit masked off by a 1,
becomes ANDED with SADDR. The “don’t cares” provide
flexibility in the user-defined addresses to address more
slaves when using the given address.
Shown in the example above, Slave 1 has been given an
address of 1111 0001 (SADDR). The SADEN byte has
been used to mask off bits to a given address to allow more
combinations of selecting Slave 1 and Slave 2. In this case
for the given addresses, the last bit (LSB) of Slave 1 is a
“don’t care” and the last bit of Slave 2 is a 1. To communi-
cate with Slave 1 and Slave 2, the master would need to
send an address with the last bit equal to 1 (e.g. 1111
0001) since Slave 1’s last bit is a don’t care and Slave 2’s
last bit has to be a 1. To communicate with Slave 1 alone,
the master would send an address with the last bit equal to
0 (e.g. 1111 0000), since Slave 2’s last bit is a 1. See the
table below for other possible combinations.
If the user added a third slave such as the example below:
Slave 1
Slave 2
Slaves 1 and 2
Given Address
Given Address
1111 0X0X
1111 0XX1
Slave 3
SADDR = 1111 1001
SADEN = 1111 0101
GIVEN
Slave 2
SADDR =
SADEN =
GIVEN
Select Slaves 1 and 2
Select Slave 1 Only
Select Slave 2 Only
= 1111 X0X1
= 1111 0XX1
Possible Addresses
1111 0011
1111 1001
FlashFlex51 MCU
Possible Addresses
Possible Addresses
1111 0001
1111 0101
1111 0000
1111 0100
1111 0111
1111 0011
S71255-05-000
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