SST89V58RD Silicon Storage Technology, SST89V58RD Datasheet - Page 67

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SST89V58RD

Manufacturer Part Number
SST89V58RD
Description
FlashFlex51 MCU
Manufacturer
Silicon Storage Technology
Datasheet

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FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
TABLE 14-7: DC Electrical Characteristics for SST89V5xRD2/RD
©2006 Silicon Storage Technology, Inc.
Symbol
V
V
V
V
V
V
V
V
V
I
I
I
R
C
I
IL
TL
LI
DD
IL
IH
IH1
OL
OL
OL1
OH
OH1
BOD
RST
IO
1. Under steady state (non-transient) conditions, I
2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the V
3. Load capacitance for Port 0, ALE and PSEN#= 100pF, load capacitance for all other outputs = 80pF.
Maximum I
Maximum I
Maximum I
If I
listed test conditions.
due to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations.
In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable
to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
OL
exceeds the test condition, V
Parameter
Input Low Voltage
Input High Voltage
Input High Voltage (XTAL1, RST)
Output Low Voltage (Ports 1.5, 1.6, 1.7)
Output Low Voltage (Ports 1, 2, 3)
Output Low Voltage (Port 0, ALE, PSEN#)
Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)
Output High Voltage (Port 0 in External Bus Mode)
Brown-out Detection Voltage
Logical 0 Input Current (Ports 1, 2, 3)
Logical 1-to-0 Transition Current (Ports 1, 2, 3)
Input Leakage Current (Port 0)
RST Pull-down Resistor
Pin Capacitance
Power Supply Current
IAP Mode
@ 33 MHz
Active Mode
@ 33 MHz
Idle Mode
@ 33 MHz
Power-down Mode
OL
OL
OL
T
per port pin:
per 8-bit port:
total for all outputs: 71mA
A
= -40°C to +85°C; V
6
15mA
26mA
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the
DD
1
= 2.7-3.6V; V
OL
must be externally limited as follows:
1,3
5
4
4
67
SS
= 0V
0.45 < V
T
T
A
Test Conditions
A
@ 1 MHz, 25°C
2.7 < V
2.7 < V
2.7 < V
= -40°C to +85°C
I
I
I
I
I
I
I
= 0°C to +70°C
OL
OL
OL
OL
OL
I
I
I
OH
OH
I
V
V
V
V
V
OH
OH
OH
V
OL
V
DD
DD
DD
DD
DD
IN
= 100µA
= 1.6mA
= 3.5mA
= 200µA
= 3.2mA
= -200µA
= -3.2mA
IN
= 16mA
= -10µA
= -30µA
= -60µA
IN
= 0.4V
= 2.7V
= 2.7V
= 2.7V
= 2.7V
= 2.7V
DD
DD
DD
= 2V
< V
< 3.6
< 3.6
< 3.6
DD
2
2
2
2
2
-0.3
OL
s of ALE and Ports 1 and 3. The noise
0.2V
V
V
V
V
V
0.7V
DD
DD
DD
DD
DD
2.35
Min
-0.5
DD
- 0.3
- 0.7
- 1.5
- 0.3
- 0.7
DD
+ 0.9
V
V
S71255-05-000
DD
DD
Max
0.45
0.45
2.55
-650
±10
225
0.7
1.0
0.3
1.0
0.3
-75
15
47
30
21
45
55
+ 0.5
+ 0.5
Data Sheet
T14-7.1 1255
Units
mA
mA
mA
µA
µA
µA
µA
µA
pF
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
5/06

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