MC10E1652 ON Semiconductor, MC10E1652 Datasheet

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MC10E1652

Manufacturer Part Number
MC10E1652
Description
DUAL ECL OUTPUT COMPARATOR WITH LATCH
Manufacturer
ON Semiconductor
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual ECL Output Comparator
With Latch
MC10E1651 and thus the MC1651 in the MECL III
fabricated using Motorola’s advanced MOSAIC III
compatible with 10H logic devices. In addition, the device is available in
both a 16-pin DIP and a 20-pin surface mount package. However, the
MC10E1652 provides user programmable hysteresis.
ECL 10H
MC10E1652 acts as a comparator, hence Q will be at a logic high level if
V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When
the latch enable input goes to a low logic level, the outputs are latched in
their present state, providing the latch enable setup and hold time
constraints are met. The level of input hysteresis is controlled by applying
a bias voltage to the HYS pin.
12/93
Motorola, Inc. 1996
Typical 3.0 dB Bandwidth > 1.0 GHz
Typical V to Q Propagation Delay of 775 ps
Typical Output Rise/Fall of 350 ps
Common Mode Range –2.0 V to +3.0 V
Individual Latch Enables
Differential Outputs
Programmable Input Hysteresis
The MC10E1652 is functionally and pin-for-pin compatible with the
The latch enable (LEN a and LEN b ) input pins operate from standard
LEN a
LEN b
logic levels. When the latch enable is at a logic high level the
HYS
V1a
V2a
V1b
V2b
LOGIC DIAGRAM
V CC = +5.0 V
V EE = –5.2 V
2–1
Qa
Qa
Qb
Qb
process and is output
family, but is
REV 1
LEN
H
H
L
MC10E1652
DUAL ECL OUTPUT
COMPARATOR
FUNCTION TABLE
CERAMIC PACKAGE
WITH LATCH
PLASTIC PACKAGE
CASE 775-02
CASE 620-10
FN SUFFIX
L SUFFIX
V1 > V2
V1 < V2
V1, V2
X
Function
Latched
H
L

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MC10E1652 Summary of contents

Page 1

... ECL 10H logic levels. When the latch enable logic high level the MC10E1652 acts as a comparator, hence Q will logic high level if V1 > V2 (V1 is more positive than V2 the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state, providing the latch enable setup and hold time constraints are met ...

Page 2

... MC10E1652 Pinout: 20-Lead PLCC (Top View) Qb LEN b NC V1b V2b GND GND LEN a NC V2a V1a ABSOLUTE MAXIMUM RATINGS (Beyond which device life may be impaired) Symbol Characteristic VSUP Total Supply Voltage | ...

Page 3

... The slew rate is 0.3 V/NS for input rising edges. The timing diagram (Figure 3) is presented to illustrate the MC10E1652’s compare and latch features. When the signal on the LEN pin logic high level, the device is operating in the “compare mode,” and the signal on the input arrives at the output after a nominal propagation delay (t PHL , t PLH ) ...

Page 4

... MC10E1652 requirement to effect the correct input-output relationship. Note that the LEN waveform in Figure 3 shows the LEN signal swinging around a reference labeled VBB INT ; this waveform emphasizes the requirement that LEN follow typical ECL 10KH logic levels because VBB INT is the internally generated reference level, hence is nominally at the ECL VBB level ...

Page 5

... U 0.350 0.356 V 0.042 0.048 W 0.042 0.048 X 0.042 0.056 Y — 0.020 0.310 0.330 K1 0.040 — 2–5 MC10E1652 – 0.010 (0.250 – 0.007 (0.180 – 0.007 (0.180 –M S ...

Page 6

... MC10E1652 - -T- SEATING PLANE 0.25 (0.010) M MOTOROLA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V - 0.25 (0.010 2–6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. ...

Page 7

... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 *MC10E1652/D* 2–7 MC10E1652 MC10E1652/D MOTOROLA ...

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