MC12439FN Motorola, MC12439FN Datasheet
MC12439FN
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MC12439FN Summary of contents
Page 1
... The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de–assertion of the PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments. 1/97 Motorola, Inc. 1997 1 REV 3 MC12439 ...
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... LVCMOS input that forces the FOUT output to synchronously reduce its frequency by a factor of 16. FREF_EXT Int. Pulldown LVCMOS input which can be used as the PLL reference frequency. XTAL_SEL Int. Pullup LVCMOS input that selects between the XTAL and FREF_EXT PLL reference inputs. A HIGH selects the XTAL input. MOTOROLA V CC TEST GND ...
Page 3
... For computer applications another useful frequency base would be 16.666MHz. From this reference one can generate a family of output frequencies at multiples of the 33.333MHz PCI clock example to generate a 533.333MHz clock 3 MC12439 +3.3 or 5.0V PLL_V CC +3.3 or 5.0V V CC0 25 24 FOUT 23 FOUT 20 TEST LATCH 3–BIT SR 22 48, so M[8:0] = 0110000. MOTOROLA ...
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... S_LOAD M[6: N[1:0] P_LOAD MOTOROLA configuration stream not configurable through the parallel interface. Although it is possible to select the node that represents FOUT, the CMOS output may not be able to toggle fast enough for some of the higher output frequencies. The T2, T1 and T0 control bits are preset to ‘000’ when P_LOAD is LOW so that the PECL FOUT outputs are as jitter– ...
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... MC12439 FOUT N DIVIDE ( (VIA ENABLE GATE) 7 TEST TEST MUX 0 Max Unit Condition 3.3 to 5.0V 0 3.3 to 5.0V 1 Continuous Current –0.8mA, (Note 2.) 0 0.8mA, (Note 2.) 2. 3.3V (Notes 3., 4.) 1. 3.3V (Notes 3., 4.) 110 mA 20 MOTOROLA ...
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... Maximum frequency on FREF_EXT is a function of the internal M counter limitations. The phase detector can handle up to 100MHz on the input, but the M counter must remain in the valid range See Applications Information section for additional information – 2.0V pulldown. MOTOROLA Min Max S_CLOCK ...
Page 7
... The parallel capacitor combination shown ensures that a low impedance path to ground exists Value for frequencies well above the bandwidth of the PLL. PLL_VCC MC12439 VCC Figure 5. Power Supply Filter 7 MC12439 to meet the voltage drop criteria. The 3. =10– 0.01 F 0.01 F MOTOROLA ...
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... Special attention should be paid to the layout of the crystal to MOTOROLA ensure a stable, jitter free interface between the crystal and the on–board oscillator. Although the MC12439 has several design features to ...
Page 9
... ECL devices. Note that if a larger swing is desired the 12439 could drive a single gate ECLinPS Lite amplifier like the MC100LVEL16. The LVEL16 will speed up the output edge rates and produce a full swing ECL output at 800MHz. 9 MC12439 Spec Limit N=1 600 700 800 MOTOROLA ...
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... PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MOTOROLA OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) ...
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... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...