MC145151 Motorola, MC145151 Datasheet - Page 29

• Manufacturer Part Number: MC145151
• Description: Parallel-Input PLL Frequency Synthesizer
• Manufacturer: Motorola

CRYSTAL OSCILLATOR CONSIDERATIONS
erence frequency to Motorola’s CMOS frequency synthe-
sizers.
Use of a Hybrid Crystal Oscillator
oscillators (TCXOs) or crystal–controlled data clock oscilla-
tors provide very stable reference frequencies. An oscillator
capable of sinking and sourcing 50 A at CMOS logic levels
may be direct or dc coupled to OSC in . In general, the highest
frequency capability is obtained utilizing a direct–coupled
square wave having a rail–to–rail (V DD to V SS ) voltage
swing. If the oscillator does not have CMOS logic levels on
the outputs, capacitive or ac coupling to OSC in may be used.
OSC out , an unbuffered output, should be left floating.
oscillators, please consult the latest version of the eem Elec-
tronic Engineers Master Catalog, the Gold Book, or similar
publications.
Design an Off–Chip Reference
ICs specifically developed for crystal oscillator applications,
such as the MC12061 MECL device. The reference signal
from the MECL device is ac coupled to OSC in . For large am-
plitude signals (standard CMOS logic levels), dc coupling is
used. OSC out , an unbuffered output, should be left floating.
In general, the highest frequency capability is obtained with a
direct–coupled square wave having rail–to–rail voltage
swing.
Use of the On–Chip Oscillator Circuitry
propriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 10.
ing capacitance, C L , which does not exceed 32 pF for fre-
quencies to approximately 8.0 MHz, 20 pF for frequencies in
the area of 8.0 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping varia-
tions in stray and IC input/output capacitance, and realistic
MOTOROLA
The following options may be considered to provide a ref-
Commercially available temperature–compensated crystal
For additional information about TCXOs and data clock
The user may design an off–chip crystal oscillator using
The on–chip amplifier (a digital inverter) along with an ap-
For V DD = 5.0 V, the crystal should be specified for a load-
Figure 10. Pierce Crystal Oscillator Circuit
* May be deleted in certain cases. See text.
OSC in
C1
R f
C2
R1*
SYNTHESIZER
FREQUENCY
OSC out
C L values. The shunt load capacitance, C L , presented
across the crystal can be estimated to be:
portion or all of C1 variable. The crystal and associated com-
ponents must be located as close as possible to the OSC in
and OSC out pins to minimize distortion, stray capacitance,
stray inductance, and startup stabilization time. In some
cases, stray capacitance should be added to the value for C in
and C out .
crystal, R e , in Figure 12. The drive level specified by the crys-
tal manufacturer is the maximum stress that a crystal can
withstand without damage or excessive shift in frequency. R1
in Figure 10 limits the drive level. The use of R1 may not be
necessary in some cases (i.e., R1 = 0 ).
overdrive the crystal, monitor the output frequency as a func-
tion of voltage at OSC out . (Care should be taken to minimize
loading.) The frequency should increase very slightly as the
dc supply voltage is increased. An overdriven crystal will de-
crease in frequency or become unstable with an increase in
supply voltage. The operating supply voltage must be re-
duced or R1 must be increased in value if the overdriven
condition exists. The user should note that the oscillator
start–up time is proportional to the value of R1.
CMOS inverters, many crystal manufacturers have devel-
oped expertise in CMOS oscillator design with crystals. Dis-
cussions with such manufacturers can prove very helpful
(see Table 1).
C1 and C2 = external capacitors (see Figure 10)
where
The oscillator can be “trimmed” on–frequency by making a
Power is dissipated in the effective series resistance of the
To verify that the maximum dc supply voltage does not
Through the process of supplying crystals for use with
1
NOTE: Values are supplied by crystal manufacturer
Figure 11. Parasitic Capacitances of the Amplifier
C out = 6 pF (see Figure 11)
C in = 5 pF (see Figure 11)
C O = the crystal’s holder capacitance
C a = 1 pF (see Figure 11)
Figure 12. Equivalent Crystal Networks
(parallel resonant crystal).
C L =
(see Figure 12)
C in
2
C in + C out
C in C out
MC145151–2 through MC145158–2
1
1
+ C a + C o + C1 C2
C a
R e
R S
X e
C out
C O
L S
C1 + C2
2
C S
2
29