MC145170-1 Motorola, MC145170-1 Datasheet - Page 10

• Manufacturer Part Number: MC145170-1
• Description: PLL FREQUENCY SYNTHESIZER WITH SERIAL INTERFACE
• Manufacturer: Motorola

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DataSheet
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C register. If desired, PD out can be forced to the high–impe–
dance state by utilization of the disable feature in the C regis-
ter (patented).
Double–Ended Phase/Frequency Detector Outputs
(Pins 14, 15)
loop error signal. Through use of a Motorola patented tech-
nique, the detector’s dead zone has been eliminated. There-
fore, the phase/frequency detector is characterized by a
linear transfer function. The operation of the phase/fre-
quency detector is described below and is shown in Fig-
ure 17.
tive pulses, R = essentially high
tially high, R = negative pulses
tially high, except for a small minimum time period when both
pulse low in phase
tive pulses, V = essentially high
tially high, V = negative pulses
tially high, except for a small minimum time period when both
pulse low in phase
MC145170–1
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R and V
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This output can be enabled, disabled, and inverted via the
These outputs can be combined externally to generate a
POL bit (C7) in the C register = low (see Figure 14)
Frequency of f V > f R or Phase of f V Leading f R : V = nega-
Frequency of f V < f R or Phase of f V Lagging f R : V = essen-
Frequency and Phase of f V = f R : V and R remain essen-
POL bit (C7) = high
Frequency of f V > f R or Phase of f V Leading f R : R = nega-
Frequency of f V < f R or Phase of f V Lagging f R : R = essen-
Frequency and Phase of f V = f R : V and R remain essen-
ENB
CLK
D in
NOTE: This initialization sequence must be used immediately after power up if control of the CLK pin is not possible. That
POWER
is, if CLK (pin 7) toggles or floats upon power up, use the above sequence to reset the device.
Also, use this sequence if power is momentarily interrupted such that the supply voltage to the device is reduced
to below 2.5 V, but not down to 0 V (for example, the supply drops down to 1 V). This is necessary because the
on–chip power–on reset is only activated when the supply ramps up from 0 V.
UP
1
ZEROES
2
3
4
CARES
DON’T
Figure 13. Reset Sequence
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1
ZEROES
changed via the C register (patented).
LD
Lock Detector Output (Pin 11)
going pulses when the loop is locked (f R and f V of the same
phase and frequency). The output pulses low when f V and f R
are out of phase or different frequencies (see Figure 17).
(patented). Upon power up, on–chip initialization circuitry
disables LD to a static low logic level to prevent a false “lock”
signal. If unused, LD should be disabled and left open.
POWER SUPPLY
V DD
Most Positive Supply Potential (Pin 16)
V SS using low–inductance capacitor(s) mounted very close
to the device. Lead lengths on the capacitor(s) should be
minimized. (The very fast switching speed of the device
causes current spikes on the power leads.)
V SS
Most Negative Supply Potential (Pin 12)
the V SS pin is tied to a ground plane.
2
These outputs can be enabled, disabled, and inter-
This output is essentially at a high level with narrow low–
This output can be enabled and disabled via the C register
This pin may range from + 2.5 to 5.5 V with respect to V SS .
For optimum performance, V DD should be bypassed to
This pin is usually ground. For measurement purposes,
3
ONE
4
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ZERO
5
DON’T CARES
MOTOROLA