MC14LC5480 Motorola, MC14LC5480 Datasheet - Page 16
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MC14LC5480
Manufacturer Part Number
MC14LC5480
Description
5 V PCM Codec-Filter
Manufacturer
Motorola
Datasheet
1.MC14LC5480.pdf
(24 pages)
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NOTES:
MC14LC5480
16
DIGITAL SWITCHING CHARACTERISTICS FOR IDL MODE
(V DD = 5.0 V
IDLE SYNC
IDL CLOCK
1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level.
2. In IDL mode, both transmit and receive 8–bit PCM words are accessed during the B1 channel, or both transmit and receive 8–bit PCM words
Ref.
No.
(BCLKT)
31
32
33
34
35
36
37
38
39
40
41
are accessed during the B2 channel as shown in Figure 5. IDL accesses must occur at a rate of 8 kHz (125 s interval).
IDL RX
IDL TX
(FST)
(DR)
(DT)
32
33
Time Between Successive IDL Syncs
Hold Time of IDL SYNC After Falling Edge of IDL CLK
Setup Time of IDL SYNC Before Falling Edge IDL CLK
IDL Clock Frequency
IDL Clock Pulse Width High
IDL Clock Pulse Width Low
Data Valid on IDL RX Before Falling Edge of IDL CLK
Data Valid on IDL RX After Falling Edge of IDL CLK
Falling Edge of IDL CLK to High–Z on IDL TX
Rising Edge of IDL CLK to Low–Z and Data Valid on IDL TX
Rising Edge of IDL CLK to Data Valid on IDL TX
5%, T A = – 40 to + 85 C, C L = 150 pF, See Figure 5 and Note 1)
40
37
1
MSB
MSB
32
2
CH1
CH1
41
3
CH2
CH2
38
4
CH3
CH3
35
5
ST1
ST1
36
Characteristics
6
ST2
ST2
Figure 5. IDL Interface Timing
7
ST3
ST3
34
8
LSB
LSB
9
40
31
39
10
11
37
MSB
MSB
12
CH1
CH1
13
CH2
CH2
41
14
38
CH3
CH3
15
ST1
ST1
16
ST2
ST2
17
39
ST3
ST3
Min
256
20
60
50
50
20
75
10
10
—
18
LSB
LSB
Note 2
19
4096
Max
50
60
50
—
—
—
—
—
—
MOTOROLA
1
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
2