ISL12025 Intersil Corporation, ISL12025 Datasheet - Page 19

• Manufacturer Part Number: ISL12025
• Description: Real-Time Clock/Calendar
• Manufacturer: Intersil Corporation

Acknowledge Polling
Disabling of the inputs during non-volatile write cycles can
be used to take advantage of the typical 5ms write cycle
time. Once the stop condition is issued to indicate the end of
the master’s byte load operation, the ISL12025 initiates the
internal non-volatile write cycle. Acknowledge polling can
begin immediately. To do this, the master issues a start
condition followed by the Memory Array Slave Address Byte
for a write or read operation (AEh or AFh). If the ISL12025 is
still busy with the non-volatile write cycle, then no ACK will
be returned. When the ISL12025 has completed the write
operation, an ACK is returned and the host can proceed with
the read or write operation. See the flow chart in
Figure 24. Note: Do not use the CCR Slave byte (DEh or
DFh) for Acknowledge Polling.
Read Operations
There are three basic read operations: Current Address
Read, Random Read, and Sequential Read.
Current Address Read
Internally the ISL12025 contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power-up, the sixteen bit address is initialized to 0h. In this
way, a current address read immediately after the power-on
reset can download the entire contents of memory starting at
the first location. Upon receipt of the Slave Address Byte
with the R/W bit set to one, the ISL12025 issues an
SIGNALS FROM
THE SLAVE
SIGNALS FROM
THE MASTER
SDA BUS
ADDRESS POINTER ENDS
6 BYTES
FIGURE 21. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10
ADDRESS = 5
AT ADDR = 5
A
R
S
T
T
19
1
ADDRESS
SLAVE
1
1
1
0
A
C
K
FIGURE 22. PAGE WRITE SEQUENCE
0 0 0 0 0 0 0
ADDRESS 1
WORD
ISL12025
A
C
K
ADDRESS 0
acknowledge, then transmits eight data bits. The master
terminates the read operation by not responding with an
acknowledge during the ninth clock and issuing a stop
condition. See Figure 23 for the address, acknowledge, and
data transfer sequence.
SIGNALS FROM
THE MASTER
SDA BUS
WORD
SIGNALS FROM
THE SLAVE
ADDRESS
FIGURE 23. CURRENT ADDRESS READ SEQUENCE
10
A
C
K
1
1
DATA
≤
≤
(1)
S
A
R
T
T
n
n
6 BYTES
1
≤
≤
16 for EEPROM array
8 for CCR
ADDRESS
SLAVE
1
ADDRESS
1
1
15
1
DATA
A
C
K
(n)
DATA
A
C
K
October 18, 2006
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