ISL29010 Intersil Corporation, ISL29010 Datasheet - Page 5

• Manufacturer Part Number: ISL29010
• Description: Light-to-Digital Output Sensor
• Manufacturer: Intersil Corporation

Register Set
There are eight registers that are available in the ISL29010. Table 1 summarizes the available registers and their functions.
Command Register 00(hex)
The Read/Write command register has five functions:
b1xxx_xxxx
bx1xx_xxxx
1. Enable; Bit 7.This function either resets the ADC or
2. ADCPD; Bit 6. This function puts the device in a
3. Timing Mode; Bit 5. This function determines whether the
ADDRESS
ADDR
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00h
01h
04h
05h
06h
07h
enables the ADC in normal operation. A logic 0 disables
ADC to reset-mode. A logic 1 enables ADC to normal
operation.
power-down mode. A logic 0 puts the device in normal
operation. A logic 1 powers down the device.
integration time is done internally or externally. In Internal
Timing Mode, integration time is determined by an
internal dual speed oscillator (f
(n = 4, 8, 12, 16) counter inside the ADC. In External
Timing Mode, integration time is determined by the time
between three consecutive external-sync sync_I
pulses commands.
BIT 7
BIT 6
0
1
0
1
MSB TIMER
REG NAME
COMMAND
LSB TIMER
CONTROL
SENSOR
SENSOR
TABLE 2. WRITE ONLY REGISTERS
MSB
LSB
REGISTER
sync_I
Disable ADC-core to reset-mode (default)
Enable ADC-core to normal operation
Normal operation (default)
Power Down
clar_int
NAME
TABLE 3. ENABLE
2
TABLE 4. ADCPD
C
ADCE
S15
T15
S7
T7
7
0
Writing a logic 1 to this address bit
ends the current ADC-integration
and starts another. Used only with
External Timing Mode.
Writing a logic 1 to this address bit
clears the interrupt.
5
FUNCTIONS/DESCRIPTION
OPERATION
OPERATION
OSC
ADCPD
S14
T14
S6
T6
6
0
), and the n-bit
TIMM
S13
T13
S5
T5
5
0
2
TABLE 1. REGISTER SET
C
ISL29010
S12
T12
S4
T4
4
0
0
* n = 4, 8, 12,16 depending on the number of clock cycles
function.
4. Photodiode Select Mode; Bits 3 and 2. Setting Bit 3 and
5. Width; Bits 1 and 0. This function determines the number
BITS 3:2
ADCM1
BITS 1:0
GAIN1
Bit 2 to 1 and 0 enables ADC to give light count DATA
output.
of clock cycles per conversion. Changing the number of
clock cycles does more than just change the resolution of
the device. It also changes the integration time, which is
the period the device’s analog-to-digital (A/D) converter
samples the photodiode current signal for a lux
measurement.
TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3
BIT 5
S11
BIT
T11
0:0
0:1
1:0
1:1
S3
T3
3
0:0
0:1
1:0
1:1
0
1
Disable ADC
Disable ADC
Light count DATA output in signed (n - 1) bit *
No operation.
Internal Timing Mode. Integration time is internally
timed determined by f
clock cycles.
External Timing Mode. Integration time is externally
timed by the I
ADCM0
GAIN0
2
2
2
2
S10
T10
S2
16
12
8
4
T2
2
= 256
= 16
TABLE 5. TIMING MODE
= 65,536
= 4,096
TABLE 7. WIDTH
NUMBER OF CLOCK CYCLES
2
RES1
C host.
S1
S9
T1
T9
0
1
OPERATION
OSC
MODE
, R
RES0
EXT
S0
S8
T0
T8
0
0
, and number of
February 13, 2008
DEFAULT
00h
00h
00h
00h
00h
00h
FN6414.0