ISL57403IN Intersil Corporation, ISL57403IN Datasheet

ISL57403IN

Manufacturer Part Number

ISL57403IN

Description

3V Dual 10-Bit/ 20/40/60MSPS A/D Converter with Internal Voltage Reference

Manufacturer

Intersil Corporation

Datasheet

1.ISL57403IN.pdf (12 pages)

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Ordering Information

3V Dual 10-Bit, 20/40/60MSPS A/D

Converter with Internal Voltage Reference

The ISL5740 is a monolithic, dual 10-bit analog-to-digital

converter fabricated in an advanced CMOS process. It is

designed for high speed applications where integration,

bandwidth and accuracy are essential. The ISL5740

features a 9-stage pipeline architecture. The fully pipelined

architecture and an innovative input stage enable the

ISL5740 to accept a variety of input conﬁgurations, single-

ended or fully differential. Only one external clock is

necessary to drive both converters and an internal band-gap

voltage reference is provided. This allows the system

designer to realize an increased level of system integration

resulting in decreased cost and power dissipation.

The ISL5740 has excellent dynamic performance while

consuming less than 280mW power at 60MSPS. The A/D

only requires a single +3.0V power supply. Data output

latches are provided which present valid data to the output

bus with a latency of 5 clock cycles.

The ISL5740 is offered in 20MSPS, 40MSPS and 60MSPS

sampling rates.

ISL5740/2IN

ISL5740/3IN

ISL5740/4IN

ISL5740/6IN

ISL5740 EVAL

NUMBER

PART

P R E L I M I N A R Y

-40 to 85 48 Ld LQFP

RANGE

TEMP.

(

Evaluation Platform

PACKAGE

3-1

1-888-INTERSIL or 321-724-7143

Data Sheet

Q48.7x7

PKG. NO.

SAMPLIN

G RATE

(MSPS)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil and Design is a trademark of Intersil Corporation.

Features

• Sampling Rate . . . . . . . . . . . . . . . . . . . . . .20/40/60MSPS

• 9.1 Bits at f

• Low Power at 60MSPS. . . . . . . . . . . . . . . . . . . . . .280mW

• Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6mW

• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 400MHz

• SFDR at f

• Excellent Channel-to-Channel Isolation . . . . . . . . . . .75dB

• On-Chip Sample and Hold Ampliﬁers

• Internal Bandgap Voltage Reference . . . . . . . . . . . . 1.25V

• Single Supply Voltage Operation . . . . . . . . . .+2.7V - 3.6V

• TTL/CMOS(3V) Digital Inputs CMOS Digital Outputs

• Offset Binary or Two’s Complement Digital Data Output

• Dual 10-Bit A/D Converters on a Monolithic Chip

• Pin Compatible Upgrade to AD9288

Pinout

• Wireless Local Loop

• PSK and QAM I&Q Demodulators

• Medical Imaging and Instrumentation

• Wireless Communications Systems

• Battery Powered Instruments

Pinout

ROUT

GND

DFS

Format

RIN

June 2000

= 10MHz . . . . . . . . . . . . . . . . . . . . . . . . .70dB

13 14 15 16

= 10MHz

File Number

Intersil Corporation 2000

ISL5740

4821.2

ID1

ID0

GND

QD0

QD1

Related parts for ISL57403IN

ISL57403IN Summary of contents

Page 1

... IN DFS IV RIN V ROUT QV RIN GND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | Intersil and Design is a trademark of Intersil Corporation. ISL5740 June 2000 File Number = 10MHz IN = 10MHz . . . . . . . . . . . . . . . . . . . . . . . . .70dB ...

Page 2

Functional Block Diagram I I S/H 2-BIT FLASH + - X2 2-BIT FLASH + - X2 2-BIT FLASH V ROUT REFERENCE I/QV RIN 3-2 ISL5740 STAGE 1 2-BIT DAC DIGITAL DELAY STAGE 8 DIGITAL ERROR CORRECTION ...

Page 3

Typical Application Schematic 0 0.1 F BNC 3-3 ISL5740 ISL5740 (LSB) ID0 (35) ( ID1 (36) ID2 (37) (3) I ...

Page 4

Pin Descriptions PIN NO. NAME DESCRIPTION 1 A Analog Ground GND 2 I I-Channel Positive Analog Input IN I-Channel Negative Analog Input IN- 4 DFS Data Format Select (Low for Offset Binary and High for Twos Complement Output ...

Page 5

Absolute Maximum Ratings Supply Voltage AGND or DGND . . . . . . . . . . . DGND to AGND . . . . . . . . ...

Page 6

Electrical Speciﬁcations 10pF PARAMETER ANALOG INPUT Maximum Peak-to-Peak Differential Analog Input Range (I I Maximum Peak-to-Peak Single-Ended Analog Input Range Analog Input Resistance IN+ IN- Analog ...

Page 7

Electrical Speciﬁcations 10pF PARAMETER Sample Clock Pulse Width (High) Sample Clock Duty Cycle Variation POWER SUPPLY CHARACTERISTICS Analog Supply Voltage Digital Supply Voltage, DV and DV CC1 CC2 Supply Current Total, I ...

Page 8

Timing Waveforms ANALOG INPUT CLOCK INPUT INPUT S/H 1ST STAGE 2ND STAGE 9TH ...

Page 9

DIFFERENTIAL INPUT CODE CENTER DESCRIPTION 1 +Full Scale (+ LSB LSB LSB LSB LSB S ...

Page 10

Figure 1). This time delay is speciﬁed as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. ...

Page 11

I +0.5V) and will be at negative full scale when I equal 0. -0.5V). Sufﬁcient headroom must be provided such that the input voltage ...

Page 12

... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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