ISL6261 Intersil, ISL6261 Datasheet
ISL6261
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ISL6261 Summary of contents
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... When the CPU enters deeper sleep mode, the ISL6261 enables diode emulation to maximize the efficiency at light load. Asserting the FDE pin of the ISL6261 in deeper sleep mode will further decrease the switching frequency at light load and increase the regulator efficiency. ...
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... LD QFN FDE 1 2 RBIAS NTC GND PAD (BOTTOM) SOFT 6 OCSET COMP ISL6261 (48 LD QFN GND PAD (BOTTOM ...
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... Nominal Channel Frequency Adjustment Range AMPLIFIERS Droop Amplifier Offset Error Amp DC Gain (Note 3) 3 ISL6261 Thermal Information Thermal Resistance (Typical) Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s +300°C Recommended Operating Conditions Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ± ...
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... Severe Overvoltage Threshold OCSET Reference Current OC Threshold Offset Undervoltage Threshold (VDIFF-SOFT) LOGIC THRESHOLDS VR_ON, DPRSLPVR and PGD_IN Input Low VR_ON, DPRSLPVR and PGD_IN Input High 4 ISL6261 = 5V -10°C to +100°C, Unless Otherwise Specified. (Continued SYMBOL TEST CONDITIONS GBW C = 20pF L SR ...
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... CLK_EN# High Output Voltage CLK_EN# Low Output Voltage NOTES: 3. Guaranteed by characterization. 4. Guaranteed by design. Gate Driver Timing Diagram PWM www.DataSheet4U.com UGATE LGATE ISL6261 = 5V -10°C to +100°C, Unless Otherwise Specified. (Continued SYMBOL TEST CONDITIONS I Logic input is low IL I Logic input is high IH ...
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... PGD_IN RBIAS VR_TT# OCSET FDE Forced diode emulation enable signal. Logic high of FDE with logic low of DPRSTP# forces the ISL6261 to operate in diode emulation mode with an increased VW-COMP voltage window. PGD_IN Digital Input. Suggest connecting to MCH_PWRGD, which www.DataSheet4U.com indicates that VCC_MCH voltage is within regulation. ...
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... The lower-side MOSFET gate signal. VCCP 5V power supply for the gate driver. www.DataSheet4U.com 7 ISL6261 NC Not connected. Ground this pin in the practical layout. VID0, VID1, VID2, VID3, VID4, VID5, VID6 VID input with VID0 as the least significant bit (LSB) and VID6 as the most significant bit (MSB). ...
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... Function Block Diagram www.DataSheet4U.com 8 ISL6261 FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6261 FN9251.1 September 27, 2006 ...
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... Simplified Application Circuit for DCR Current Sensing VR_TT# VID<0:6> DPRSTP# DPRSLPVR MCH_PWRGD CLK_ENABLE# VR_ON IMVP6_PWRGD VCC-SENSE VSS-SENSE www.DataSheet4U.com FIGURE 2. ISL6261-BASED IMVP-6® SOLUTION WITH INDUCTOR DCR CURRENT SENSING 9 ISL6261 3V3 VDD VCCP R 5 RBIAS VIN R 6 NTC C 5 UGATE ...
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... Simplified Application Circuit for Resistive Current Sensing VR_TT# VID<0:6> DPRSTP# DPRSLPVR MCH_PWRGD CLK_ENABLE# VR_ON IMVP6_PWRGD VCC-SENSE VSS-SENSE www.DataSheet4U.com FIGURE 3. ISL6261-BASED IMVP-6® SOLUTION WITH RESISTIVE CURRENT SENSING 10 ISL6261 +3 3V3 VDD VCCP R 5 RBIAS VIN R 6 NTC C 5 UGATE ...
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... When using inductor DCR current sensing, an NTC thermistor is used to compensate the positive temperature coefficient of the copper winding resistance to maintain the load-line accuracy. The switching frequency of the ISL6261 controller is set by the resistor R Figures 2 and 3. 10mV/us Vboot ...
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... ISL6261 TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION VID6 VID1 VID0 Vo ( 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 ...
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... TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATIONAL MODES OF ISL6261 www.DataSheet4U.com DPRSTP# 0 Control 0 Signal 0 Logic 1 13 ISL6261 TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION VID1 VID0 Vo (V) VID6 0 0 0.4500 ...
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... FET current flows from source to drain, it turns synchronous FET to reduce the conduction loss. When the current reverses its direction trying to flow from drain to source, the ISL6261 turns off the low-side FET to prevent the output capacitor from discharging through the inductor, therefore eliminating the extra conduction loss ...
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... When connected to the SOFT pin, I get a larger current, labelled I Specification Table, on the SOFT pin. I with a minimum of 175μA. The IMVP-6 associated with regulating the output voltage. SLEWRATE internal current SOFT SS . The ISL6261 controls the output voltage slew rate Internal to ISL6261 Error Ampliflier C ...
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... SOFT Selecting Rbias To properly bias the ISL6261, a reference current needs to be derived by connecting a 147k, 1% tolerance resistor from the RBIAS pin to ground. This provides a very accurate 10μA current source from which OCSET reference current is derived. Caution should used in layout: This resistor should be placed in the close proximity of the RBIAS pin and be connected to good quality signal ground ...
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... ISL6261 Figure 7 shows the circuitry associated with the thermal throttling feature of the ISL6261. At low temperature, SW1 is on and SW2 connects to the 1.20V side. The total current going into the NTC pin is 60µA. The voltage on the NTC pin is higher than 1.20V threshold voltage and the comparator output is low ...
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... − kΩ NTC 1 μ ISL6261 Once − ) (EQ 273 T is the o is 25°C. For most One example of using Equations 10, 11 and 12 to design a o thermal throttling circuit with the temperature hysteresis 100°C to 105°C is illustrated as follows. Since T ...
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... FIGURE 9. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DCR SENSING Static Mode of Operation - Static Droop Using DCR Sensing The ISL6261 has an internal differential amplifier to accurately regulate the voltage at the processor die. For DCR sensing, the process to compensate the DCR resistance variation takes several iterative steps. Figure 2 shows the DCR sensing method ...
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... ISL6261 (R in Figure 2) sets the The droop capacitor refers designed correctly, its voltage will be a high-bandwidth analog voltage of the inductor current correctly, its voltage will be distorted from the actual (EQ ...
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... ISL6261 The user can choose the actual resistor and capacitor values based on the recommendation and input them in the spreadsheet, then see the actual loop gain curves and the regulator output impedance curve ...
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... FIGURE 13. AN EXAMPLE OF ISL6261 COMPENSATION SPREADSHEET 22 ISL6261 FN9251.1 September 27, 2006 ...
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... OC Internal to ISL6261 1 FIGURE 14. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DISCRETE RESISTOR SENSING Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) www.DataSheet4U.com FIGURE 15. CCM EFFICIENCY, VID = 1.1V 8V 12.6V AND V IN1 IN2 FIGURE 17. DEM EFFICIENCY, VID = 0.7625V 8V 12.6V AND V IN1 IN2 23 ISL6261 10uA ...
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... Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued) FIGURE 19. ENHANCED DEM EFFICIENCY, VID = 0.7625V 8V 12.6V AND V IN1 IN2 FIGURE 21. ENHANCED DEM EFFICIENCY, VID = 1.1V 8V 12.6V AND V IN1 IN2 www.DataSheet4U.com 5V/div 0.5V/div 10V/div FIGURE 23. SOFT-START 19V 0A, VID = 1.5V, IN Ch1: VR_ON, Ch2: Vo, Ch4: PHASE ...
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... Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued) 5V/div 0.2V/div 5V/div 10V/div FIGURE 25 VID 19V 2A, VID = 1.5V, BOOT IN Ch1: PGD_IN, Ch2: Vo, Ch3: CLK_EN#, Ch4: PHASE 5V/div 0.5V/div 7.5ms 5V/div 10V/div FIGURE 27. CLK_EN AND PGOOD ASSERTION DELAY, V =19V, Io=2A, VID=1.1V, Ch1: CLK_EN#, www ...
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... Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued) FIGURE 31. C4 ENTRY/EXIT HFM VID = 1.1V, LFM VID = 0.9V, C4 VID = 0.7625V, FDE = DPRSLPVR, Ch1: DPRSTP#, Ch2: Vo, Ch3: DPRSLPVR/FDE, Ch4: PHASE 100A/us www.DataSheet4U.com FIGURE 33. LOAD STEP UP RESPONSE IN CCM 8V 20A at 100A/us, VID = 1.1V, ...
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... Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued) 100A/us FIGURE 37. LOAD TRANSIENT RESPONSE IN ENHANCED DEM 8V Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE 120us FIGURE 39. OVERCURRENT PROTECTION 28A, VID = 1.1V, Ch1: DROOP-VO (2.1mV = 1A), Ch2: Vo, Ch3: PGOOD, www.DataSheet4U.com Ch4: PHASE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’ ...
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... ISL6261 Eval1 Rev. C Evaluation Board Schematic 100 R47 10K R42 10K R41 10K R40 10K R38 10K R37 10K R36 10K R32 P33 P31 P28 P27 P25 P24 P23 P20 P19 P18 P16 www.DataSheet4U.com P13 28 ISL6261 10UF 10 R46 C31 J1 10UF C30 ...
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... ISL6261 Eval1 Rev. C Evaluation Board Schematic 330UF C89 330UF C41 330UF C40 P38 P37 C5B 10UF C5 C4 www.DataSheet4U.com P35 29 ISL6261 22UF C70 22UF 22UF 22UF C64 C65 C66 22UF 22UF 22UF C58 C59 C60 22UF 22UF 22UF 330UF C52 C53 C54 ...
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... ISL6261 Eval1 Rev. C Evaluation Board Schematic VSS AE4 VSS AE8 VSS AE11 VSS AE14 VSS AE16 VSS AE19 VSS AE23 VSS AE26 VSS AF3 VSS AF6 VSS AF8 VSS AF11 VSS AF13 VSS AF16 VSS AF19 VSS AF21 VSS AF24 www.DataSheet4U.com ...
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... ISL6261 Eval1 Rev. C Evaluation Board Schematic www.DataSheet4U.com J11 J12 31 ISL6261 (Continued) 3 0.12 R76 0 R75 49.9K 3 R71 10UF C81 2 FN9251.1 September 27, 2006 ...
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... ISL6261 Eval1 Rev. C Evaluation Board Schematic 1X3 www.DataSheet4U.com 10K R99 10K R96 10K R93 10K R90 10K R87 10K R84 10K R81 32 ISL6261 (Continued) BAV99 15PF C87 P45 15PF P43 P42 BAV99 C85 0.01UF 1 C79 ...
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... Package Outline Drawing L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 9/06 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( www.DataSheet4U.com TYPICAL RECOMMENDED LAND PATTERN 33 ISL6261 6. ± 36X 40X 40X NOTES ...
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... Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 9/06 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( www.DataSheet4U.com TYPICAL RECOMMENDED LAND PATTERN 34 ISL6261 7. ± 44X 48X 48X NOTES: 4X 5.5 44X 0. 48X 0 . 40± ...