ISL6421A Intersil Corporation, ISL6421A Datasheet
ISL6421A
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ISL6421A Summary of contents
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... Voltage Regulator with I C Interface for Advanced Satellite Set-top Box Designs The ISL6421A is a highly integrated solution for providing power and control signals from advanced satellite set-top box (STB) modules to the low noise block (LNB). The internal architecture of this device contains a current-mode ...
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Block Diagram OVERCURRENT COUNTER PROTECTION LOGIC SCHEME 1 PWM LOGIC GATE Q PGND ILIM CS AMP CS COMPENSATION COMP FB VSW VOUT ON CHIP VCC LINEAR UVLO SGND POR SOFT-START INT 5V SOFT-START EN SEL18V OLF DCL OC CLK S ...
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Typical Application Schematic NOTE: SGND and PGND to be shorted as close layout ...
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... TONE Tone Frequency Tone Amplitude Tone Duty Cycle Tone Rise or Fall Time 4 ISL6421A Thermal Information Thermal Resistance (Notes 1, 2) QFN Package Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -40°C to 150°C For recommended soldering conditions, see Tech Brief TB389. ...
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... Bypass capacitor for internal 5V. DSQIN When HIGH this pin enables the internal 22kHz modulation for the LNB, Use this pin for tone enable function for the LNB. 5 ISL6421A = -20°C to +85°C, unless otherwise noted. Typical values are SYMBOL TEST CONDITIONS ...
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... CPSWOUT SEL18V When connected HIGH, this pin will change the output of the PWM to 18V. Only available on the QFN package option. Functional Description The ISL6421A is a single output voltage regulator controlled bus, making it an ideal choice for advanced satellite set-top box and personal video recorder applications ...
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... Philips I = 20ms. During Data transmission from the main microprocessor to the ISL6421A and vice versa takes place through the 2 wires bus interfaces, which consists of the two lines SDA and OFF SCL. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor ...
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... SDA line remains at the HIGH level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer. The ISL6421A will not generate the acknowledge if the POWER OK signal from the UVLO is LOW. SCL ...
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... Received Data ( Bus Read Mode The ISL6421A can provide to the master a copy of the 2 System Register information via the I The read mode is Master activated by sending the chip address with R/W bit set the following Master generated clock bits, the ISL6421A issues a byte on the SDA data bus line (MSB transmitted first) ...
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... I (mA) OUT FIGURE 4. EFFICIENCY vs LOAD CURRENT 22kHz TONE (0.1V/DIV) 10µs/DIV FIGURE 6. 22kHz TONE VOUT (20mV/DIV) VPWM (20mV/DIV) 2µs/DIV FIGURE 8. RIPPLE VOUT = 14.0V 10 ISL6421A 450.0 550.0 8.0 TONE & VOUT (1V/DIV) DSQIN (1V/DIV) FIGURE 7. 22kHz TONE MODULATED BY DSQIN ...
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... IOUT (0.2A/DIV) 0.5ms/DIV FIGURE 10. DYNAMIC RESPONSE VOUT = 19.0V VGATE (2V/DIV) VDRAIN (10V/DIV) 2µs/DIV FIGURE 12. GATE AND DRAIN WAVEFORMS VOUT = 19.0V 11 ISL6421A (Continued) VOUT (1V/DIV) VPWM (1V/DIV) IOUT (0.2A/DIV) FIGURE 11. DYNAMIC RESPONSE VOUT = 14.0V VGATE (2V/DIV) VDRAIN (10V/DIV) FIGURE 13. GATE AND DRAIN WAVEFORMS VOUT = 14.0V 0.5ms/DIV 2µ ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 ISL6421A L32.5x5 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C ...