ISL6524A Intersil Corporation, ISL6524A Datasheet - Page 8

• Manufacturer Part Number: ISL6524A
• Description: VRM8.5 PWM and Triple Linear Power System Controller
• Manufacturer: Intersil Corporation

voltage ramp-up. At time T4, all output voltages are within
power-good limits, situation reported by the PGOOD pin
going high.
The T2 to T3 time interval is dependent upon the value of
C
up time of the OUT1 and OUT3 voltages. If selecting a
different capacitor then recommended in the circuit application
literature, consider the effects the different value will have on
the ramp-up time and inrush currents of the OUT1 and OUT3
outputs.
Fault Protection
All four outputs are monitored and protected against extreme
overload. The chip’s response to an output overload is
selective, depending on the faulting output.
An over-voltage on V
1, 2, and 3, and latches the IC off. An under-voltage on
V
on output 1, or an under-voltage event on output 2 or 3,
increments the respective fault counters and triggers a
shutdown of outputs 1, 2, and 3, followed by a soft-start re-
start. After three consecutive fault events on either counter,
the chip is latched off. Removal of bias power resets both
the fault latch and the counters. Both counters are also reset
by a successful start-up of all the outputs.
Figure 7 shows a simplified schematic of the fault logic. The
over-current latches are set dependent upon the states of
3.0V
10V
SS13
OUT4
0V
0V
T0
. The same capacitor is also responsible for the ramp-
output latches the IC off. A single over-current event
SS24
T1
ATX 12V
ATX 3.3V
ATX 5V
FIGURE 6. SOFT-START INTERVAL
V
T2
OUT4
OUT1
(1.8V)
T3
output (VSEN1) disables outputs
TIME
VTTPG
V
T4
8
OUT3
PGOOD
T5
(1.5V)
SS13
V
V
OUT1
OUT2
(1.65V)
(1.2V)
the over-current (OC1), output 2 and 3 under-voltage (UV2,
UV3) and the soft-start signals (SS13, SS24). Window
comparators monitor the SS pins and indicate when the
respective C
signals). An under-voltage on either linear output (VSEN2,
VSEN3, or VSEN4) is ignored until the respective UP signal
goes high. This allows V
without fault at start-up. Following an over-current event
(OC1, UV2, or UV3 event), bringing the SS24 pin below 0.8V
resets the over-current latch and generates a soft-started
ramp-up of the outputs 1, 2, and 3.
OUT1 Over-Voltage Protection
During operation, a short across the PWM upper MOSFET
(Q1) causes V
the over-voltage threshold of 120% of DACOUT, the over-
voltage comparator trips to set the fault latch and turns the
lower MOSFET (Q2) on as needed to regulate the output
voltage to the 120% threshold. This operation typically
results in the blow of the input fuse, subsequent discharge of
V
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), the output level
is monitored for voltages above 1.3V. Should VSEN1
exceed this level, the lower MOSFET, Q2, is driven on.
Over-Current Protection
All outputs are protected against excessive over-currents.
The PWM controller uses the upper MOSFET’s on-
resistance, r
against a shorted output. All linear regulators monitor their
OC1
SS24
UV3
SS13
OV
UV4
UV2
OUT1
0.8V
4V
4V
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
.
SS13UP
DS(ON)
SS
OUT1
SS24UP
pins are fully charged to above 4.0V (UP
to monitor the current for protection
to increase. When the output exceeds
LATCH
S
R
OC
OUT3
Q
LATCH
R
S
OC
Q
POR
and V
R
COUNTER
OUT4
COUNTER
to increase
R
INHIBIT1,2,3
FAULT
LATCH
S
R
Q
Q
SSDOWN
FAULT