ISL6525 Intersil Corporation, ISL6525 Datasheet - Page 7

• Manufacturer Part Number: ISL6525
• Description: Buck and Synchronous-Rectifier Pulse-Width Modulator (PWM) Controller
• Manufacturer: Intersil Corporation

Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
amplifier (Error Amp) output (V
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V
PHASE node. The PWM wave is smoothed by the output filter
(L
The modulator transfer function is the small-signal transfer
function of V
Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage V
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6525) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high
gain peak do to the high Q factor of the output filter and is
not shown in Figure 8. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
capabilities of the error amplifier. The Closed Loop Gain is
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
O
F
F
OUT
F
Z1
Z2
LC
and C
FB
) is regulated to the Reference voltage level. The error
=
=
=
. The goal of the compensation network is to provide
-------------------------------------- -
2
----------------------------------
2
----------------------------------------------------- -
2
O
ST
ND
ST
ND
).
0dB
OUT
R2 C1
R1
1
L
1
Zero Below Filter’s Double Pole (~75% F
Pole at the ESR Zero
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
) and adequate phase margin. Phase margin
O
/V
+
1
R3
E/A
C
O
LC
. This function is dominated by a DC
and a zero at F
C3
O
and C
7
F
E/A
ESR
F
F
P1
P2
OSC
) is compared with the
=
O
=
=
), with a double pole
-------------------------------------------- -
2
.
----------------------------------
2
ESR
------------------------------------------------------ -
2
P2
IN
R3 C3
ESR C
. The DC Gain of
with the
R2
1
) divided by the
1
IN
1
at the
--------------------- -
C1
C1 C2
O
0dB
+
C2
LC
and
IN
)
ISL6525
constructed on the log-log graph of Figure 8 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the
transient and slow the current load rate seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (effective series resistance) and
voltage rating requirements rather than actual capacitance
requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1.0 F
ceramic capacitors in the 1206 surface-mount package.
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
100
-20
-40
-60
80
60
40
20
0
and Z
10
(R2/R1)
20LOG
MODULATOR
IN
to provide a stable, high bandwidth (BW) overall
100
GAIN
1K
Pentium® is a registered trademark of Intel Corporation.
F
Z1
F
FREQUENCY (Hz)
LC
F
Z2
10K
F
P1
F
(V
ESR
IN
100K
20LOG
F
/ V
P2
OSC
OPEN LOOP
ERROR AMP GAIN
1M
)
COMPENSATION
GAIN
CLOSED LOOP
GAIN
10M