ISL6539 Intersil Corporation, ISL6539 Datasheet - Page 16

• Manufacturer Part Number: ISL6539
• Description: Wide Input Range Dual PWM Controller with DDR Option
• Manufacturer: Intersil Corporation

The inductor copper loss can be significant in the total
system power loss. Attention has to be given to the DCR
selection. Another factor to consider when choosing the
inductor is its saturation characteristics at elevated
temperature. Saturated inductors could result in nuisance
OC, or OV trip.
Output voltage ripple and the transient voltage deviation are
factors that have to be taken into consideration when
selecting an output capacitor. In addition to high frequency
noise related MOSFET turn-on and turn-off, the output
voltage ripple includes the capacitance voltage drop and
ESR voltage drop caused by the AC peak-to-peak current.
These two voltages can be represented by:
These two components constitute a large portion of the total
output voltage ripple. Several capacitors have to be
paralleled in order to reduce the ESR and the voltage ripple.
If the output of the converter has to support another load
with high pulsating current, such as the first channel in
Figure 2, it feeds into the VTT channel which draws high
pulsating current. More capacitors are needed in order to
reduce the equivalent ESR and suppress the voltage ripple
to a tolerable level.
To support a load transient that is faster than the switching
frequency, more capacitors have to be used to reduce the
voltage excursion during load step change. Another aspect
of the capacitor selection is that the total AC current going
through the capacitors has to be less than the rated RMS
current specified on the capacitors, to prevent the capacitor
from overheating.
For DDR applications, as the second channel draws pulsate
current directly from the first channel, it is recommended to
parallel capacitors for output of the first channel to reduce
ESR and smooth ripple. Excessive high ripple voltage at the
output can propagate into the output of the error amplifier
and cause too much phase voltage jitter.
Input Capacitor Selection
When the upper MOSFET is on, the current in the output
inductor will be seen by the input capacitor. Even though this
current has a triangular shaped top, its RMS value can be
fairly approximated by:
This RMS current includes both DC and AC components.
Since the DC component is the product of duty cycle and
load current, the AC component can be approximated by:
∆V
∆V
lin
linac V
rms
c
esr
=
(
(
=
V
------------------ -
8CF
IN
IN
I
I
)
pp
pp
)
=
sw
ESR
=
D V
D V
(
(
IN
IN
) D V
)*I
–
load
(
IN
16
)
2
I
load
ISL6539
AC components will be provided from the input capacitor.
The input capacitor has to be able to handle this ripple
current without overheating and with tolerable voltage ripple.
In addition to the capacitance, a ceramic capacitor is
generally used between the drain terminal of the upper
MOSFET and the source terminal of the lower MOSFET, in
order to clamp the parasitic voltage ringing at the phase
node in switching.
Choosing MOSFETs
For a maximum input voltage of 15V, at least a minimum 30V
MOSFETs should be used. The design has to trade off the
gate charge with the r
• For the lower MOSFET, before it is turned on, the body
• In the turning off process of the lower MOSFET, the load
This results in much less switching loss of the lower
MOSFETs.
The duty cycle is often very small in high battery voltage
applications, and the lower MOSFET will conduct most of
the switching cycle; therefore, the lower the r
lower MOSFET, the less the power loss. The gate charge for
this MOSFET is usually of secondary consideration.
The upper MOSFET does not have this zero voltage
switching condition, and because the upper MOSFET
conducts for less time compared to the lower MOSFET, the
switching loss tends to be dominant. Priority should be given
to the MOSFETs with less gate charge, so that both the gate
driver loss, and switching loss, will be minimized.
For the lower MOSFET, its power loss can be assumed to be
the conduction loss only.
For the upper MOSFET, its conduction loss can be written as:
and its switching loss can be written as:
The peak and valley current of the inductor can be obtained
based on the inductor peak-to-peak current and the load
current. The turn-on and turn-off time can be estimated with
the given gate driver parameters in the Electrical
Specification Table on page 4. For example, if the gate driver
turn-on path MOSFET has a typical on-resistance of 4Ω, its
maximum turn-on current is 1.2A with 5V Vcc. This current
P
P
P
lower
uppercond
uppersw
diode has been conducting. The lower MOSFET driver will
not charge the miller capacitor of this MOSFET.
current will shift to the body diode first. The high dv/dt of
the phase node voltage will charge the miller capacitor
through the lower MOSFET driver sinking current path.
(
V
IN
(
V
)
(
IN
≈
V
IN
(
)
1 D V
=
)
–
=
V
--------------------------------------------- -
IN
(
D V
(
I
IN
vally
DSON
IN
)
)I
2
)I
load
T
load
on
of the MOSFET:
F
2
r
2
sw
DS ON
r
DS ON
+
(
(
V
---------------------------------------------- -
IN
)Lower
)upper
I
peak
2
T
DSON
off
F
sw
of the