ISL6556A Intersil Corporation, ISL6556A Datasheet - Page 13

• Manufacturer Part Number: ISL6556A
• Description: Optimized Multi-Phase PWM Controller with 6-Bit DAC for VR10.X Application
• Manufacturer: Intersil Corporation

Load-Line Regulation
Some microprocessor manufacturers require a precisely-
controlled output resistance. This dependence of output
voltage on load current is often termed “droop” or “load line”
regulation. By adding a well controlled output impedance,
the output voltage can be level in the direction that works to
control the voltage spike coincident with fast load current
demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 5, a current proportional to the average
current in all active channels, I
load-line regulation resistor, R
across R
creating an output voltage droop with a steady-state value
defined as
In most cases, each channel uses the same R
sense current. A more complete expression for V
derived by combining equations 4 and 5.
Output-Voltage Offset Programming
The ISL6556A allows the designer to accurately adjust the
offset voltage. When a resistor, R
OFS and VCC, the voltage across it is regulated to 2.0V.
This causes a proportional current (I
R
regulated to 0.5V, and I
between DAC and REF, R
product (I
These functions are shown in Figures 6 and 7.
As evident in Figure 7, the OFSOUT pin must be connected
to the REF pin for this current injection to function in
ISL6556ACR. The current flowing through R
offset at the REF pin, which is ultimately duplicated at the
output of the regulator.
Once the desired output offset voltage has been determined,
use the following formulae to set R
For Positive Offset (connect R
V
V
R
OFS
DROOP
DROOP
OFS
is connected to ground, the voltage across it is
=
FB
OFS
--------------------------
V
2 R
=
=
OFFSET
is proportional to the output current, effectively
I
I
-------------
AVG
OUT
N
x R
REF
R
REF
r
---------------------- R
DS ON
R
FB
ISEN
) is equal to the desired offset voltage.
OFS
REF
FB
flows out of OFS. A resistor
13
FB
OFS
AVG
, is selected so that the
. The resulting voltage drop
OFS
, flows from FB through a
OFS
to VCC):
OFS
, is connected between
:
) to flow into OFS. If
REF
ISEN
DROOP
creates an
(EQ. 7)
value to
(EQ. 5)
(EQ. 6)
is
ISL6556A
For Negative Offset (connect R
R
OFS
R
R
FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING
REF
OFS
FIGURE 6. OUTPUT VOLTAGE OFFSET PROGRAMMING
GND
VCC
DAC
REF
OFS
=
or
0.5 R
------------------------------
2.0V
V
OFFSET
ISL6556ACB
WITH ISL6556ACR (32-LEAD QFN)
VCC
+
-
WITH ISL6556ACB (28-LEAD SOIC)
REF
DYNAMIC
VID D/A
0.5V
E/A
GND
+
-
FB
OFS
FB
GND
DYNAMIC
to GND):
VID D/A
+
-
ISL6556ACR
E/A
0.5V
VCC
+
-
2.0V
(EQ. 8)
OFS
DAC
OFSOUT
GND
VCC
or
REF
R
R
REF
OFS