ISL6595 Intersil Corporation, ISL6595 Datasheet - Page 13

• Manufacturer Part Number: ISL6595
• Description: Digital Multiphase Controller
• Manufacturer: Intersil Corporation

current for the measurement. A series and shunt resistor
network should be used to scale the resultant current to the
proper range. The current range is the same as the current
sense inputs, from 0 to 275µA in 4.3µA steps.
The ADC measurements are converted to temperature using
a programmable 4-segment piece-wise linear table while the
internal proportional-to-absolute temperature (PTAT)
reference is digitized directly, using a linear curve fit. Both
internal and external temperature measurements are
multiplexed through the current ADC at a low frequency,
providing run-time internal and external temperature
information to perform temperature compensation, reporting,
alerts, and shutdown.
Digital Control Loop and PWM Generation
The digital control loop uses a proportional, integral, and
derivative (PID) compensator to drive the digitized sense
voltage to the desired target. An additional second
derivative gain term and a 2
additional high order zeros and poles to further refine the
wideband characteristics of the loop. All loop parameters
are programmable over a wide range of values, allowing
loop bandwidths of 10-300kHz to be attained depending on
the number and type of power stages used.
The effective transfer function of the compensator is given
by:
where:
( H
) z
Ki, Kp, Kd, and Kd2 are the integral, proportional,
derivative, and second derivative gain terms
(HEX)
VID
=

 

2
2
2
2
2
2
3
3
3
3
3
3
3
3
1
−
HI
K
z
i
−
1
+
K
p
+
VID
K
(HEX)
d
1 (
B
A
D
C
E
F
1
0
3
2
5
4
7
6
−
LO
z
−
1
)
+
K
d
2
1 (
−
VOLTAGE
nd
z
1.59375
1.58125
1.56875
1.55625
1.54375
1.53125
1.51875
13
1.5875
1.5625
1.5375
−
1.575
1.525
1
1.55
)
(V)
1.6
order post-filter provide
2
TABLE 1. Intel® VR10 VID TABLE (WITH 6.25mV EXTENSION, Note 8)

 





1
+
K
1
+
fd
1
K
z
fd
−
1
1
+
+
K
K
VID
fd
fd
2
2
z
HI
−
2
5
5
5
5
5
5
5
5
5
5
5
6
6
6




(HEX) VID




N
ph
K
⋅
div
mod
_
sel




LO



ISL6595
V
Q
D
C
in
B
A
F
E
4
7
6
9
8
1
0
3
(HEX)



The control loop operates at the same frequency as the
voltage ADC, which is synchronous to the switching
frequency and given by:
Fs = 2 * Nph * Fsw = 156.25MHz/div_sel
The compensator digital output is converted to a pulse width
using a digital counter based pulse width modulator. The
pulse width modulator uses 2 successive samples to
modulate the leading edge and then the trailing edge of a
pulse. The modulator provides for monotonic edge
placements with a resolution of 100ps. The next 2 samples
are then used to modulate the next phase in the firing
sequence. The pulse width modulator is capable of setting a
maximum duty cycle limit, overlapping adjacent phases, a
minimum pulse width of 13ns, and also producing zero pulse
width with minimal glitching.
Voltage Identification Codes
The target voltage is provided by external parallel 8-bit
voltage identification (VID) inputs. The ISL6595 is fully
compliant with VRD/VRM 11.0 deglitching and dynamic VID
stepping requirements.
VOLTAGE
Kfd1 and Kfd2 are the coefficients of a second order all
pole low pass post-filter
Kmod is a programmable maximum duty cycle scaling
term
Nph is the number of phases and div_sel is the divider
ratio setting the switching frequency
Vin is the power stage input voltage, typically 12V
Q is the ADC step size, 3.125mV
1.33125
1.31875
1.30625
1.29375
1.28125
1.26875
1.25625
1.3125
1.2875
1.2625
1.325
1.275
1.25
(V)
1.3
VID
HI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(HEX) VID
LO
B
A
D
C
1
0
3
2
5
4
7
6
9
8
(HEX)
VOLTAGE
February 27, 2006
1.08125
1.06875
1.05625
1.04375
1.03125
1.01875
1.00625
1.0875
1.0625
1.0375
1.0125
1.075
1.025
1.05
(V)
FN9192.0