ISL6742 Intersil Corporation, ISL6742 Datasheet - Page 8

• Manufacturer Part Number: ISL6742
• Description: Advanced Double-Ended PWM Controller
• Manufacturer: Intersil Corporation

Typical Performance Curves
Pin Descriptions
VDD - VDD is the power connection for the IC. To optimize
noise immunity, bypass VDD to GND with a 0.1µF or larger
high frequency ceramic capacitor as close to the VDD and
GND pins as possible.
VDD is monitored for supply voltage undervoltage lock-out
(UVLO). The start and stop thresholds track each other
resulting in relatively constant hysteresis.
GND - Signal and power ground connections for this device.
Due to high peak currents and high frequency operation, a
low impedance layout is necessary. Ground planes and
short traces are highly recommended.
VREF - The 5.00V reference voltage output having 3%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1µF to 2.2µF low ESR capacitor.
CT - The oscillator timing capacitor is connected between
this pin and GND. It is charged through an internal 200µA
current source and discharged with a user adjustable current
source controlled by RTD.
FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE
1.02
1.01
0.99
0.98
1•10
1•10
100
1
10
-40
FIGURE 3. DEADTIME (DT) vs CAPACITANCE
4
3
0
-25
10
-10
20
5
30
TEMPERATURE (°C)
20
40
RTD (kΩ)
8
35
50
50
60
70
65
80
80
CT =
1000pF
680pF
470pF
330pF
220pF
100pF
90
95
100
110
ISL6742
RTD - This is the oscillator timing capacitor discharge
current control pin. The current flowing in a resistor
connected between this pin and GND determines the
magnitude of the current that discharges CT. The CT
discharge current is nominally 20x the resistor current. The
PWM deadtime is determined by the timing capacitor
discharge duration. The voltage at RTD is nominally 2.00V.
The minimum recommended value of RTD is 2.00kΩ.
CS - This is the input to the overcurrent comparator and the
average current sample and hold circuit. The overcurrent
comparator threshold is set at 1.00V nominal. The CS pin is
shorted to GND at the termination of either PWM output.
Depending on the current sensing source impedance, a
series input resistor may be required due to the delay
between the internal clock and the external power switch.
This delay may result in CS being discharged prior to the
power switching device being turned off.
OUTA and OUTB - These paired outputs are the pulse-
width-modulated outputs for controlling the switching FETs in
alternate sequence.
FIGURE 2. CT DISCHARGE CURRENT GAIN vs RTD CURRENT
1•10
25
24
23
22
21
20
19
18
100
10
3
0
0.1
FIGURE 4. CAPACITANCE vs FREQUENCY
200
RTD CURRENT (µA)
400
CT (nF)
1
www.DataSheet4U.com
600
800
RTD=
10kΩ
50kΩ
100kΩ
July 25, 2005
FN9183.1
1000
10