ISL6745A Intersil Corporation, ISL6745A Datasheet - Page 7

• Manufacturer Part Number: ISL6745A
• Description: Improved Bridge Controller
• Manufacturer: Intersil Corporation

Pin Descriptions
V
noise immunity, bypass V
capacitor as close to the V
The total supply current, I
applied to outputs OUTA and OUTB. Total I
sum of the quiescent current and the average output current.
Knowing the operating frequency, F
loading capacitance charge, Q, per output, the average
output current can be calculated from Equation 1:
R
control pin. A resistor is connected between this pin and
GND. The current flowing through the resistor determines
the magnitude of the discharge current. The discharge
current is nominally 55x this current. The PWM deadtime is
determined by the timing capacitor discharge duration.
C
this pin and GND.
CS - This is the input to the overcurrent protection comparator.
The overcurrent comparator threshold is set at 0.600V nominal.
The CS pin is shorted to GND at the end of each switching
cycle. Depending on the current sensing source impedance, a
series input resistor may be required due to the delay between
the internal clock and the external power switch.
Exceeding the overcurrent threshold will start a delayed
shutdown sequence. Once an overcurrent condition is
detected, the soft-start charge current source is disabled.
The soft-start capacitor begins discharging through a 15µA
current source, and if it discharges to less than 3.9V
(Sustained Overcurrent Threshold), a shutdown condition
occurs and the OUTA and OUTB outputs are forced low.
When the soft-start voltage reaches 0.27V (Reset
Threshold) a soft-start cycle begins.
If the overcurrent condition ceases, and then an additional
50µs period elapses before the shutdown threshold is
reached, no shutdown occurs. The SS charging current is
re-enabled and the soft-start voltage is allowed to recover.
GND - Reference and power ground for all functions on this
device. Due to high peak currents and high frequency
operation, a low impedance layout is necessary. Ground
planes and short traces are highly recommended.
OUTA and OUTB - Alternate half cycle output stages. Each
output is capable of 1A peak currents for driving power
MOSFETs or MOSFET drivers. Each output provides very
low impedance to overshoot and undershoot.
SS - Connect the soft-start timing capacitor between this pin
and GND to control the duration of soft-start. The value of the
capacitor determines the rate of increase of the duty cycle
I
OUT
DD
TD
T
- The oscillator timing capacitor is connected between
- This is the oscillator timing capacitor discharge current
- V
=
2 Q F
DD
•
is the power connection for the IC. To optimize
•
SW
A
DD
DD
DD
, will be dependent on the load
to GND with a ceramic
7
and GND pins as possible.
SW
, and the output
DD
current is the
(EQ. 1)
ISL6745A
during start-up, controls the overcurrent shutdown delay, and
the overcurrent and short circuit hiccup restart period.
V
error voltage is applied to this pin to control the duty cycle.
Increasing the signal level increases the duty cycle. The
node may be driven with an external error amplifier or an
opto-coupler.
V
drive. Having a separate V
circuitry from the high power gate drive noise.
Functional Description
Features
The ISL6745A PWM is an excellent choice for low cost
bridge topologies for applications requiring accurate
frequency and deadtime control. Among its many features
are 1A FET drivers, adjustable soft-start, overcurrent
protection and internal thermal protection, allowing a highly
flexible design with minimal external components.
Oscillator
The ISL6745A has an oscillator with a frequency range to
2MHz, programmable using a resistor R
The switching period may be considered to be the sum of
the timing capacitor charge and discharge durations. The
charge duration is determined by C
source (assumed to be 160µ
duration is determined by R
where T
times, respectively, T
period, and F
switching cycle requires two oscillator cycles. The actual
times will be slightly longer than calculated due to internal
propagation delays of approximately 5ns/transition. This
delay adds directly to the switching duration, and also
causes overshoot of the timing capacitor peak and valley
voltage thresholds, effectively increasing the peak-to-peak
voltage on the timing capacitor. Additionally, if very low
charge and discharge currents are used, there will be an
increased error due to the input impedance at the C
The above formulae help with the estimation of the
frequency. Practically, effects like stray capacitances that
affect the overall C
and charge current over-temperature, etc. exist, and are
best evaluated in-circuit. Equation 2 follows from the basic
capacitor current equation,
T
T
T
ERR
DDP
C
D
OSC
≈
≈
1.25
---------------------------------------------------------------------------- - R
CTDisch
- The inverting input of the PWM comparator. The
- V
=
C
×10
DDP
T
and T
C
4
+
OSC
•
T
is the separate collector supply to the gate
arg
C
D
D
T
eCurrentGain
=
1
are the approximate charge and discharge
is the oscillator frequency. One output
T
--------------- -
F
capacitance, variation in R
OSC
OSC
1
s
is the oscillator free running
DDP
TD
i
A
=
in the formula). The discharge
s
and C
C
pin helps isolate the analog
•
×
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dV
t d
T
TD
and the internal current
T
. In this case, with
•
.
C
TD
T
and capacitor C
September 11, 2008
s
TD
voltage
T
pin.
FN6703.1
(EQ. 2)
(EQ. 3)
(EQ. 4)
T
.