ISL8102 Intersil Corporation, ISL8102 Datasheet - Page 14

• Manufacturer Part Number: ISL8102
• Description: Two-Phase Buck PWM Controller
• Manufacturer: Intersil Corporation

Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime
control technique to minimize deadtime, resulting in high
efficiency from the reduced freewheeling time of the lower
MOSFET body-diode conduction, and to prevent the upper and
lower MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.3V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is released
to rise. An auto-zero comparator is used to correct the r
drop in the phase voltage preventing false detection of the
-0.3V phase level during r
case of zero current, the UGATE is released after 35ns delay of
the LGATE dropping below 0.5V. During the phase detection,
the disturbance of LGATE falling transition on the PHASE node
is blanked out to prevent falsely tripping. Once the PHASE is
high, the advanced adaptive shoot-through circuitry monitors
the PHASE and UGATE voltages during a PWM falling edge
and the subsequent UGATE turn-off. If either the UGATE falls
to less than 1.75V above the PHASE or the PHASE falls to less
than +0.8V, the LGATE is released to turn on.
Internal Bootstrap Device
The two integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V and its capacitance value can be
chosen from the following equation:
where Q
at V
control MOSFETs. The ∆V
allowable droop in the rail of the upper gate drive. Figure 10
shows the boot capacitor ripple voltage as a function of boot
capacitor value and total upper MOSFET gate charge.
C
Q
BOOT_CAP
GATE
GS1
=
G1
gate-source voltage and N
Q
---------------------------------- N
G1
is the amount of gate charge per upper MOSFET
≥
V
------------------------------------- -
∆V
⋅
GS1
PVCC
BOOT_CAP
Q
GATE
⋅
DS(ON)
Q1
BOOT_CAP
14
conduction period. In the
Q1
term is defined as the
is the number of
DS(ON)
(EQ. 11)
ISL8102
Gate Drive Voltage Versatility
The ISL8102 provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
Initialization
Prior to initialization, proper conditions must exist on the
ENLL, VCC, PVCC and the REF0 and REF1 pins. When the
conditions are met, the controller begins soft-start. Once the
output voltage is within the proper window of operation, the
controller asserts PGOOD.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL8102 is
released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL8102 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL8102 will not inadvertently turn off unless the bias
voltage drops substantially (see Electrical
Specifications).
1.6
1.4
1.2
0.8
0.6
0.4
0.2
0.0
1.
0.0
20nC
0.1
VOLTAGE
0.2
50nC
Q
GATE
0.3
= 100nC
∆V
0.4
BOOT_CAP
0.5
0.6
(V)
0.7
0.8
October 19, 2005
0.9
FN9247.0
1.0