ISL8843 Intersil Corporation, ISL8843 Datasheet - Page 9

• Manufacturer Part Number: ISL8843
• Description: Industry Standard Single-Ended Current Mode PWM Controller
• Manufacturer: Intersil Corporation

frequency. The double-pole will be critically damped if the
Q-factor is set to 1, over-damped for Q < 1, and under-
damped for Q > 1. An under-damped condition may result in
current loop instability.
Q
where D is the percent of on time during a switching cycle.
Setting Q = 1 and solving for Se yields
S
Since Sn and Se are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by Ton to obtain the voltage change that occurs during Ton.
V
where Vn is the change in the current feedback signal (∆I)
during the on time and Ve is the voltage that must be added
by the external ramp.
For a flyback converter, Vn can be solved for in terms of
input voltage, current transducer components, and primary
inductance, yielding
V
where R
switching frequency, L
minimum input voltage, and D is the maximum duty cycle.
The current sense signal at the end of the ON time for CCM
operation is:
V
where V
L
current at current limit. Equation 13 assumes the voltage
drop across the output rectifier is negligible.
Since the peak current limit threshold is 1.00V, the total
current feedback signal plus the external ramp voltage must
sum to this value when the output load is at the current limit
threshold.
V
s
e
e
e
CS
e
=
is the secondary winding inductance, and I
+
=
=
=
V
-------------------------------------------------
π m
=
S
V
D T
--------------------------------------------------- - 1
CS
(
n
n
N
------------------------ I
⋅




CS
CS
c
S




=
(
SW
1
-- -
π
1
-- -
π
N
1 D
⋅
R
+
+
P
is the voltage across the current sense resistor,
1
is the current sense resistor, T
–
1
CS
0.5
0.5
⋅
L
V
p
) 0.5
IN







–
------------ - 1
1 D
------------ - 1
1 D
O
⋅
1
–
1
–
R
+
CS
)
(
--------------------------------------------- -
1 D
p
–
–
–


is the primary inductance, V






-- -
π
) V
+
2L
⋅
0.5
s
O
9


⋅
------------ - 1
1 D
T
–
sw
1



–


SW
V
O
is the
V
is the output
IN
(EQ. 11)
(EQ. 13)
(EQ. 12)
(EQ. 10)
(EQ. 14)
(EQ. 9)
is the
ISL8843
Substituting Equations 12 and 13 into Equation 14 and
solving for R
R
Adding slope compensation is accomplished in the ISL8843
using an external buffer transistor and the RTCT signal. A
typical application sums the buffered RTCT signal with the
current sense feedback and applies the result to the CS pin
as shown in Figure 6.
Assuming the designer has selected values for the RC filter
(R6 and C4) placed on the CS pin, the value of R9 required
to add the appropriate external ramp can be found by
superposition.
V
The factor of 2.05 in Equation 16 arises from the peak
amplitude of the sawtooth waveform on RTCT minus a base-
emitter junction drop. That voltage multiplied by the
maximum duty cycle is the voltage source for the slope
compensation. Rearranging to solve for R9 yields:
R9
The value of R
rescaled so that the current sense signal presented at the
CS pin is that predicted by Equation 13. The divider created
by R6 and R9 makes this necessary.
R′
CS
e
CS
=
=
=
2.05D R6
---------------------------- -
=
(
---------------------------------------------- -
R6
2.05D V
-------------------------------------------------------------------------------------------------------------------------------------------------------- -
D T
---------------------------------
R6
--------------------- - R
⋅
+
R9
+
sw
⋅
R9
L
CS
V
FIGURE 6. SLOPE COMPENSATION
–
R9
p
R6
e
C4
⋅
R9
CS
V
e
yields
⋅
IN
) R6
⋅
determined in Equation 15 must be
CS
⋅




V
----------------- - 1
1
-- -
π
1 D
+
–
0.5
Ω
–




+
1
------ -
N
N
RTCT
CS
s
p
⋅



I
O
+
(
--------------------------------------------- -
1 D
VREF
–
) V
2L
⋅
January 3, 2006
s
O
(EQ. 15)
(EQ. 16)
(EQ. 17)
(EQ. 18)
⋅
FN9238.1
T
sw


