ISL9187 Intersil Corporation, ISL9187 Datasheet - Page 9

• Manufacturer Part Number: ISL9187
• Description: (ISL9107 / ISL9108) 1.5A 1.6MHz Low Quiescent Current High Efficiency Synchronous Buck Regulator
• Manufacturer: Intersil Corporation

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Theory of Operation
The ISL9107 and ISL9108 are step-down switching
regulators optimized for battery-powered handheld
applications. The regulators operate at typical 1.6MHz fixed
switching frequency under heavy load condition to allow
small external inductor and capacitors to be used for minimal
printed-circuit board (PCB) area. At light load, the regulators
can be selected to enter skip mode to reduce the switching
frequency, unless forced to the fixed frequency, to minimize
the switching loss and to maximize the battery life. The
quiescent current under skip mode with no loading is
typically only 17µA. The supply current is typically only
0.1µA when the regulator is disabled.
PWM Control Scheme
These devices use the peak-current-mode pulse-width
modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting. Figure 17
shows the circuit functional block diagram. The current loop
consists of the oscillator, the PWM comparator COMP,
current sensing circuit and the slope compensation for the
current loop stability. The current sensing circuit consists of
the resistance of the P-Channel MOSFET when it is turned
on and the Current Sense Amplifier (CSA). The control
reference for the current loops comes from the Error
Amplifier (EAMP) of the voltage loop.
The PWM operation is initialized by the clock from the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the P-Channel
MOSFET starts ramping up. When the sum of the CSA
output and the compensation slope reaches the control
reference of the current loop, the PWM comparator COMP
sends a signal to the PWM logic to turn off the P-Channel
MOSFET and to turn on the N-Channel MOSFET. The
N-MOSFET remains on till the end of the PWM cycle. Figure 18
shows the typical operating waveforms during the normal PWM
operation. The dotted lines illustrate the sum of the slope
compensation ramp and the CSA output.
The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a
0.8V reference voltage to the voltage control loop. The
v
v
EAMP
v
OUT
CSA
d
i
FIGURE 18. PWM OPERATION WAVEFORMS
L
9
ISL9107, ISL9108
feedback signal comes from the FB pin. The soft-start block
only affects the operation during the start-up and will be
discussed separately in “Soft Start-Up” on page 10. The
EAMP is a transconductance amplifier, which converts the
voltage error signal to a current output. The voltage loop is
internally compensated by a RC network. The maximum
EAMP voltage output is precisely clamped to the bandgap
voltage.
Skip Mode
With the MODE pin connected to logic high, the device
enters a pulse-skipping mode at light load to minimize the
switching loss by reducing the switching frequency.
Figure 19 illustrates the skip mode operation. A zero-cross
sensing circuit (as shown in Figure 17) monitors the
N-Channel MOSFET current for zero crossing. When it is
detected to cross zero for 8 consecutive cycles, the regulator
enters the skip mode. During the 8 consecutive cycles, the
inductor current could be negative. The counter is reset to
zero when the sensed N-Channel MOSFET current does not
cross zero during any cycle within the 8 consecutive cycles.
Once the device enters the skip mode, the pulse modulation
starts being controlled by the SKIP comparator shown in
Figure 17. Each pulse cycle is still synchronized by the PWM
clock. The P-Channel MOSFET is turned on at the rising
edge of clock and turned off when its current reaches 20% of
the peak current limit. As the average inductor current in
each cycle is higher than the average current of the load, the
output voltage rises cycle over cycle. When the output
voltage reaches 1.5% above it’s nominal voltage, the
P-Channel MOSFET is turned off immediately and the
inductor current is fully discharged to zero and stays at zero.
The output voltage reduces gradually due to the load current
discharging the output capacitor. When the output voltage
drops to the nominal voltage, the P-Channel MOSFET will
be turned on again, repeating the previous operations.
The regulator resumes normal PWM mode operation when
the output voltage is sensed to drop below 1.5% of its
nominal voltage value.
Enable
The enable (EN) pin allows the user to enable or disable the
converter for purposes such as power-up sequencing. With
the EN pin pulled to high, the converter is enabled, the
internal reference circuit wakes up first and then the soft
start-up begins. When the EN pin is pulled to logic low, the
converter is disabled, the P-Channel MOSFET is turned off
immediately and the output capacitor is discharged through
internal discharge path.
Undervoltage Lockout (UVLO)
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold, the device is disabled.
December 21, 2007
FN6612.0