ISL96017 Intersil Corporation, ISL96017 Datasheet - Page 7

• Manufacturer Part Number: ISL96017
• Description: 128-Tap DCP / 16kbit EEPROM and I2C Serial Interface
• Manufacturer: Intersil Corporation

Principles of Operation
This device combines a DCP, 16kbit non-volatile memory,
and an I
between a host and the DCP and memory.
DCP Description
The DCP has 10kΩ or 50kΩ nominal total resistance and
128 taps. It is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP, the RH and RL pins, are equivalent to the fixed
terminals of a mechanical potentiometer. The RW pin is
connected to intermediate nodes, and it is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by a 7-bit
volatile DCP Register. When the DCP Register contains all
zeroes (00 hex, or “R
its RL terminal. When the DCP Register contains all ones
(7F hex, or “R
terminal. As the value of the DCP Register increases from all
zeroes to all ones, the wiper moves monotonically from the
position closest to RL to the closest to RH. Therefore, the
resistance between RH and RW decreases monotonically
from R
increases monotonically from R
While the device is being powered up, the DCP Register is
reset to 40 hex (64 decimal). Soon after the power supply
voltage becomes large enough for reliable non-volatile
memory reading, the device reads the value stored on the
non-volatile Initial Value Register (IVR) and loads it into the
DCP Register.
Memory Description
This device contains 2048 non-volatile bytes organized in
128 pages of 16 bytes each. This allows writing 16 bytes on
a single I
non-volatile write cycle. The memory is accessed by I
interface operations with addresses 000 hex through 7FF hex.
Bytes at addresses 000 hex through 7FB hex are available
to the user as general purpose memory. The byte at address
7FF hex, IVR, contains the initial value loaded at power-up
into the volatile DCP Register. The byte at address 7FE hex
0
2
to R
2
C serial interface providing direct communication
C interface operation, followed by a single internal
127
127
, while the resistance between RW and RL
”), its wiper terminal is closest to its RH
0
”), its wiper terminal, RW, is closest to
Note: OV = “Only Volatile”. All other bits in register 7FEh must be 0.
Address
7FEh OV
7FDh
7FCh
7FBh D
7FFh 0
000h
7
127
to R
7
0
.
D
D
0
6
6
TABLE 1. ISL96017 MEMORY MAP
D
D
0
Data Bits
Reserved
Reserved
5
5
D
D
0
4
4
2
C
D
D
0
3
3
ISL96017
D
D
0
2
2
D
D
0
1
1
controls the access to the DCP byte (See “Access to DCP
Register and IVR”). Bytes at addresses 7FC hex and 7FD
hex, are reserved, which means that they should not be
written, and their value should be ignored if they are read.
(See Table 1).
Access to DCP Register and IVR
The volatile DCP Register and the non-volatile (IVR) can be
read or written directly using the I
Address Byte 07FF hex.
The MSB of the byte at address 7FE hex is called
“OnlyVolatile” and controls the access to the DCP Register
and IVR. This bit is volatile and it’s reset to “0” at power up.
The Data Byte read from memory address 7FF hex, is from
the DCP register when the “OnlyVolatile” bit is “1”, and from
the IVR when this bit is “0”.
The Data Byte of a Write operation to memory address 7FF
hex is written only to the DCP Register when the
“OnlyVolatile” bit is “1”, and it’s written to both the DCP
Register and the IVR when this bit is “0”.
When writing to the “OnlyVolatile” bit at address 7FE hex,
the seven LSBs of the Data Byte must be all zeros.
Writing to address 7FE hex and 7FF hex can be done in two
Write operations, or one Write operation with two Data
Bytes.
See next sections for interface protocol description.
D
D
0
0
0
General Purpose Memory
Access Control
IVR, DCP
Function
2
C serial interface, with
April 17, 2006
FN8243.1