ISL98003 Intersil, ISL98003 Datasheet
ISL98003
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ISL98003 Summary of contents
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... Automatic Black Level Compensation (ABLC™) eliminates part-to-part offset variation, ensuring perfect black level performance in every application. The ISL98003's Digital PLL generates a pixel clock from the analog source's HSYNC or SOG (Sync-On-Green) signals. Pixel clock output frequencies range from 10MHz to 165MHz with sampling clock jitter of 250ps peak-to-peak ...
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... ISL98003CNZ-110 ISL98003CNZ-150 ISL98003CNZ-165 ISL98003CNZ-EVALZ Evaluation Platform NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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... Operating Conditions Temperature Range ISL98003INZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C ISL98003CNZ 0°C to +70°C Supply Voltage Range . . . . . . . . . . . . . . . . . 3.3V ±10%, 1.8V ±10% CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. ...
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... Electrical Specifications Specifications apply for V pixel rate = 110MHz for ISL98003-110, 150MHz for ISL98003-150 and 165MHz for ISL98003-165 25MHz, and T XTAL SYMBOL PARAMETER Offset Adjustment Range (ABLC Enabled or Disabled) ANALOG VIDEO INPUT CHARACTERISTICS (R Input Range Input Bias Current Input Capacitance Full Power Bandwidth ...
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... Electrical Specifications Specifications apply for V pixel rate = 110MHz for ISL98003-110, 150MHz for ISL98003-150 and 165MHz for ISL98003-165 25MHz, and T XTAL SYMBOL PARAMETER V Analog Supply Voltage, 1.8V A1.8 V Digital Supply Voltage, 3.3V D3.3 V Digital Supply Voltage, 1.8V D1.8 I Analog Supply Current, 3.3V A3.3 (Note 4) IPLL A3.3 I Analog Supply Current, 1.8V A1.8 (Note 4) I Digital Supply Current, 3.3V D3 ...
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... YUV Output Data Timing and Latency HSYNC IN ANALOG VIDEO IN DATACLK G[7:0] R[7:0] B[7:0] HS OUT 6 ISL98003 t HOLD t SETUP THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED TO. THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST OF THE AFE’S OUTPUT SIGNALS ...
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... COAST Digital 3.3V input. When this input is high and external COAST is selected, the PLL will coast, ignoring all transitions on IN the active channel’s HSYNC/SOG. 7 ISL98003 ISL98003 (80 LD EPTQFP) TOP VIEW ...
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... Power supply for the digital PLL section. Connect to a 1.8V supply and bypass to GND with 0.1µF. D1.8 DTEST1 For production use only. Tie to GND. 8 ISL98003 DESCRIPTION GND . Take low for at least 1µs and then high again to reset the ISL98003. This D supply. D centered around 0.5V. P-P centered around 0.5V. P ...
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Sync Flow 3 165 MHZ CH0 3 TRIPLE 8- BIT 3 CH1 AFE SOG SLICER A SOG0 SOG1 SOG SLICER B HSYNC SLICER A HSYNC0 HSYNC1 HSYNC SLICER B VSYNC SLICER A VSYNC0 VSYNC1 VSYNC SLICER B CH0 AND CH1 ...
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... Selected Input Channel Characteristics, (read only) 0x02 CH0 and CH1 Activity Status, (read only) 0x03 Not Used (read only) 10 ISL98003 BITS FUNCTION NAME 1:0 SYNC Type 00: Automatic Sync Selection logic could not find good sync SOG (Automatic Sync mode only). 01: SYNC on HSYNC/VSYNC ...
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... ADDRESS (DEFAULT VALUE) 0x04 Interrupt Status, Write each bit to clear it, 0xFF to clear all. 0x05 Interrupt Mask Register, (0xFF) 11 ISL98003 BITS FUNCTION NAME 0 CH0 Sync Changed 0: No change 1: CH0 activity or polarity changed 1 CH1 Sync Changed 0: No change 1: CH1 activity or polarity changed ...
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... Green Gain LSB, (0x00) 0x16 Blue Gain MSB, (0x55) 0x17 Blue Gain LSB, (0x00) 0x18 Red Offset MSB, (0x80) 0x19 Red Offset LSB, (0x00) 12 ISL98003 BITS FUNCTION NAME 1:0 Input Channel Select Sets video muxes as well as HSYNC, VSYNC, and SOG input muxes. 0: CH0 1: CH1 2: N/A ...
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... DC-Restore and ABLC starting pixel MSB, (0x00) 0x25 DC-Restore and ABLC starting pixel LSB, (0x02) 0x26 DC-Restore Clamp Width, (0x10) 13 ISL98003 BITS FUNCTION NAME 7:0 Green Offset MSB ABLC off: upper 8 bits to Green offset DAC ABLC enabled: Green digital offset (See Red Offset) 5:0 ...
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... REGISTER ADDRESS (DEFAULT VALUE) 0x27 ABLC Configuration, (0x40) 0x28 Output Format 1, (0x00) 14 ISL98003 BITS FUNCTION NAME 0 ABLC Disable 0: ABLC on (default) - use 8-bit digital offset control. 0x000 = -0x200 LSB offset, 0x3FF = +0x1FF LSB offset, 0x200 = 0x000 LSB offset. 1: ABLC off - use 8-bit offset DACs, bypass digital adder (add/subtract nothing, but keep same delay through channel) ...
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... Output Signal Disable, (0xFF) Note: All digital outputs are tri-stated by default to ease multiplexing with other AFEs 0x2C Power Control, (0x00) 15 ISL98003 BITS FUNCTION NAME 0 DATACLK Polarity 0: Pixel data changes on falling edge (default) 1: Pixel data changes on rising edge 1 FIELD output polarity 0: Odd = low, Even = high (default) ...
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... All values referred to voltage at HSYNC input pin, 300mV hysteresis 0x30 SOG Slicer Thresholds, (0x66) 16 ISL98003 BITS FUNCTION NAME 4:0 Crystal Clock Frequency Crystal clock frequency in MHz (decimal). 0x00: Test Mode, Do not use. 0x01 - 0x0A: 10MHz, APLL DIV = 35 (0x23) 0x0B: 11MHz, APLL DIV = 32 ...
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... HSYNC Period LSB, (read only) 0x42 HSYNC Width MSB, (read only) 0x43 HSYNC Width LSB, (read only) 17 ISL98003 BITS FUNCTION NAME 3:0 Glitch Filter Width 0: 16 crystal clocks 1: 17 crystal clocks 2: 1 crystal clocks 3: 2 crystal clocks 4: 3 crystal clocks (default) ...
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... Measurement Configuration, (0x00) AUTO ADJUST REGISTERS 0x50 Phase ADJ CMD FN, (0x00) 0x51 Phase ADJ STATUS, (read only) 18 ISL98003 BITS FUNCTION NAME 3:0 VSYNC Period MSB These bit report a 12-bit value containing the width of one frame (= 2 fields for interlaced field for progressive) of video. 7:0 ...
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... Horizontal pixel mask 1, (0x01) 0x54 Horizontal pixel mask 2, (0x01) 0x55 Phase Adjust Command Options, (0x20) 19 ISL98003 BITS FUNCTION NAME 2:0 PADJ Exclude v2 Vertical line mask: How many lines to exclude before the leading edge of VSYNC 000: 0 lines 001: 1 lines (default) 010: 2 lines ...
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... Phase Adjust Data 0, (read only) 0x60 AFE CTRL, (0x00) 0x61 ADC CTRL, (0x00) 20 ISL98003 BITS FUNCTION NAME 7:0 PADJ Threshold Threshold of transitions visible for capturing. These are the 8 MSBs of the 8-bit threshold word used for phase quality measurements. The actual 8-bit threshold used equals the value in this register times 4 ...
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... Technical Highlights The ISL98003 provides all the features of traditional triple channel video AFEs, but adds several next-generation enhancements, bringing performance and ease of use to new levels. DPLL All video AFEs must phase lock to an HSYNC signal, supplied either directly or embedded in the video stream (Sync On Green) ...
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... The range for each color is typically 0V to 0.7V from black to white. HSYNC and VSYNC are separate signals. Component YPbPr Inputs In addition to RGB and RGB with SOG, the ISL98003 has an option that is compatible with the component YPbPr video inputs typically generated by DVD players. While the ISL98003 digitizes signals in these color spaces, it does not perform color space conversion ...
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... SOG pulse). Inside the ISL98003, a 1µA pull-down ensures that each sync tip triggers the clamp circuit causing the tip to be clamped to a 600mV level. A comparator compares the SOG signal with an internal 4-bit programmable threshold level reference ranging from 0mV to 300mV above the sync clamp level ...
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... Sync Timing Measurement The ISL98003 analyzes the timing characteristics of the sync signals for the currently selected input channel and presents the results in registers 0x40 through 0x46. The HSYNC period and pulse width values are 16-bit ...
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... Sampling Phase to the best setting. Set register 0x50 to 0x03 to activate the auto phase adjust function. Data Enable (DE) Generator The ISL98003 provides a signal that is high during the active video time when properly configured. This signal is used by devices such as DVI/HDMI transmitters to gate the active portion of the video and ignore the H and V sync times ...
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... SOG signal, while non-standard SOG signals and TriLevel sync signals may have amplitudes below the default SOG slicer levels and not be easily detected consequence, not all of the activity detect bits in the ISL98003 are correct under all conditions. For best SOG operation, the SOG low pass filter (register 0x31[6] should always be enabled to reject the high frequency peaking often seen on video signals ...
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... If the external clock source has increased jitter, the sample clock generated by the DPLL may exhibit increased jitter as well. EMI Considerations There are two possible sources of EMI on the ISL98003, as follows. CRYSTAL OSCILLATOR The EMI from the crystal oscillator is negligible. This is due to ...
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... Data on the serial bus must be valid for the entire time SCL is high (Figure 5). To achieve this, data being written to the ISL98003 is latched on a delayed version of the rising edge of SCL. SCL is delayed and deglitched inside the ISL98003 for three crystal clock periods (120ns for a 25MHz crystal) to eliminate spurious clock pulses that could disrupt serial communication ...
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... ISL98003 Register Data Write( This is the data to be written to the ISL98003’s configuration register. Note: The ISL98003’s Configuration Register’s address pointer auto increments after each data write: repeat this step to write multiple sequential bytes of data to the Configuration Register. ...
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... This sets the initial address of the ISL98003’s configuration register for subsequent reading. Ends the previous transaction and starts a new one R/W ISL98003 Serial Bus Address Write This is the 7-bit address of the ISL98003 on the 2-wire bus. The 0 address is 0x98. R indicating next transaction(s) will read. ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 31 ISL98003 Q80.12x12 80 LEAD THIN PLASTIC QUAD FLATPACK EXPOSED PAD PACKAGE ...