ISL98012 Intersil, ISL98012 Datasheet - Page 9
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ISL98012
Manufacturer Part Number
ISL98012
Description
1.8V Input PWM Step-Up Regulator
Manufacturer
Intersil
Datasheet
1.ISL98012.pdf
(10 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISL98012IUZ
Manufacturer:
LT
Quantity:
68
The boost converter output voltage is determined by the
relationship in Equation 8:
V
where V
RC Filter
The maximum voltage rating for the VDD pin is 12V. An RC
filter is recommended to clean the output ripple before
bootstrapping the part. For bootstrapped applications with
V
the VDD pin and is given by Equation 9:
where I
can be 10Ω to 51Ω with C
Thermal Performance
The ISL98012 uses a fused-lead package, which has a
reduced θ
+115°C/W on a two-layer board. Maximizing copper around
the ground pins will improve the thermal performance.
This chip also has internal thermal shut-down set at around
+135°C to protect the component.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
R
OUT
OUT
4
=
V
-------------------- -
=
greater than 10V, R
O
DD
I
FB
DD
V
–
FB
JA
10
is shown in the I
slightly changes with V
×
of +100°C/W on a four-layer board and
⎛
⎜
⎝
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
1
+
R
------ -
R
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
2
1
⎞
⎟
⎠
For information regarding Intersil Corporation and its products, see www.intersil.com
4
4
DD
can drop V
= 0.1µF.
9
vs f
S
DD
curve. Otherwise, R
.
OUT
for coupling into
(EQ. 9)
(EQ. 8)
4
ISL98012
www.DataSheet.co.kr
Layout Considerations
The layout is very important for the converter to function
properly. power ground ( ) and signal ground (
be separated to ensure that the high pulse current in the
power ground never interferes with the sensitive signals
connected to signal ground. They should only be connected
at one point.
The trace connected to pin 8 (FB) is the most sensitive trace.
It needs to be as short as possible and in a “quiet” place,
preferably between PGND or SGND traces.
In addition, the bypass capacitor connected to the VDD pin
needs to be as close to the pin as possible.
The heat of the chip is mainly dissipated through the SGND
pin. Maximizing the copper area around it is preferable. In
addition, a solid ground plane is always helpful for the EMI
performance.
The demo board is a good example of layout based on these
principles. Please refer to the ISL98012 Technical Brief for
the layout.
http://www.intersil.com/data/tb/tb429.pdf
December 8, 2010
) should
FN6654.1
Datasheet pdf - http://www.DataSheet4U.net/