AD6641 Analog Devices, AD6641 Datasheet - Page 25

• Manufacturer Part Number: AD6641
• Description: 250 MHz Bandwidth DPD Observation Receiver
• Manufacturer: Analog Devices

Parallel Master Mode (Single Capture)
Details of the transaction diagram for parallel master mode are
shown in Figure 40 with the PD[11:0] output word. Clock cycles
are approximate because the fill and dump signals can be driven
asynchronously. In this example, PCLK± is derived from the
master clock with a divide by 8 programmed from the SPI.
Fill Pulse (1)
The FIFO captures data after a fill signal (high level) is detected
on the rising edge of the sampling clock. In synchronous opera-
tion, a valid high level is accomplished by adhering to the setup
and hold times specified. For nonsynchronous control, the fill
signal can be widened to accommodate two or more clock
cycles to guarantee capture of a high level. Fill count (0x104)
is reset on the rising edge of the clock and is incremented on
subsequent clock cycles only after the fill signal returns low. A
new fill signal at any point during the capture resets the counter
and begins filling the FIFO.
Empty Signal (2)
After the FIFO state machine has begun loading data, the
empty signal goes low 24 clock cycles after the fill signal was
last sampled high.
Full Signal (3)
The full signal indicates when the FIFO has been filled and is
driven high when the number of samples specified has been
captured in the FIFO, where
The time at which the full signal goes high is based on
(FILL_CNT + 1) × 64 + 13 clock cycles after the fill signal was
last sampled high.
Number of Samples = (FILL_CNT + 1) × 64
PD[11:0]
EMPTY
PCLK+
PCLK–
DUMP
FULL
FILL
1
2
3
4
5
Figure 40. Parallel Mode Transaction Diagram
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6
D0
Dump Signal (4)—Transition to High
The dump signal initiates reading data from the FIFO. Dump is
enabled with a high level and should be initiated only after the
full signal goes high. The dump signal should be held high until
all data has been read out of the FIFO.
PCLK± Signal (5)
The PCLK± (parallel clock) signal is configured as an output
from the device. PCLK± begins cycling 71 ADC clock cycles
after the dump signal is sampled high. PCLK± goes low after
the last data is read out of the FIFO and remains low until the
next dump operation.
PD[11:0] Signal (6)
The PD (parallel data) output provides 12 data bits (PD[11:0])
at a maximum rate of 1/8
after two PCLK± cycles (assuming the dump signal has been
sampled).
Dump Signal (7)—Transition to Low
A dump signal transition to low is applied after data has been
read out of the FIFO.
Empty Signal (8)—Transition to High
The empty signal transitions to high after data has been output
from the FIFO based on the clock cycle count of (FILL_CNT +
1) × 64. The transition occurs nine clock cycles after the last
PCLK± rising edge.
Continuous Capture Mode
The FIFO can be placed into continuous capture mode by writ-
ing the FIFO fill mode bits in the fill control register (0x101[3:2])
to 01. In the continuous capture mode, data is loaded continu-
ously into the FIFO and the FILL± pins pulsing high is used to
stop the operation. This allows the history of the samples that
preceded an event to be captured.
D8
D16
th
of the sampling clock. Data begins
7
8
AD6641