74HC4059D,112 NXP Semiconductors, 74HC4059D,112 Datasheet - Page 16
![IC PROG DIV-BY-N COUNTER 24-SOIC](/photos/6/52/65263/568-24-soic_sot137-1_sml.jpg)
74HC4059D,112
Manufacturer Part Number
74HC4059D,112
Description
IC PROG DIV-BY-N COUNTER 24-SOIC
Manufacturer
NXP Semiconductors
Series
74HCr
Datasheets
1.74HCT4046ADB112.pdf
(19 pages)
2.74HCT4046ADB112.pdf
(23 pages)
3.74HCT4059D112.pdf
(20 pages)
Specifications of 74HC4059D,112
Package / Case
24-SOIC (7.5mm Width)
Logic Type
Divide-by-N
Direction
Down
Number Of Elements
1
Number Of Bits Per Element
16
Reset
Asynchronous
Timing
Synchronous
Count Rate
43MHz
Trigger Type
Positive Edge
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-2695-5
933757410112
933757410112
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
AC CHARACTERISTICS
The “AC CHARACTERISTICS” table lists the guaranteed
limits when a device is tested under the conditions given in
the AC Test Circuits and Waveforms section.
TEST CIRCUITS
Good high-frequency wiring practices should be used in
test circuits. Capacitor leads should be as short as
possible to minimize ripples on the output waveform
transitions and undershoot. Generous ground metal
(preferably a ground-plane) should be used for the same
reasons. A V
decoupling capacitor should be provided
CC
at the test socket, also with short leads. Input signals
should have rise and fall times of 6 ns, a signal swing of
0 V to V
for 74HC and 0 V to 3 V for 74HCT; a 1.0 MHz
CC
square wave is recommended for most propagation delay
tests. The repetition rate must be increased for testing
f
. Two pulse generators are usually required for testing
max
such parameters as set-up time, hold time and removal
time. f
is also tested with 6 ns input rise and fall times,
max
with a 50% duty factor, but for typical f
as high as
max
60 MHz, there are no constraints on rise and fall times.
March 1988
16