VT1621M VIA, VT1621M Datasheet - Page 19

• Manufacturer Part Number: VT1621M
• Description: TV Encoder
• Manufacturer: VIA

Serial bus Interface
Both VT1621 and VT1621M contain a standard serial bus
control port through which the control registers can be written
and read. The serial bus address is 40h.
CRTC
Normally the VGA controller supplies the horizontal and
vertical sync signals. However, they could be generated either
by the VT1621 or the VT1621M. This module generates the
horizontal and vertical sync signals. In CCIR656 input mode,
the embedded sync may also be used.
PLL
Both VT1621 and VT1621M contain a high accuracy, low-
jitter phase-locked-loop to create outstanding quality video.
Normal operation requires the encoding clock to be generated
by the PLL. In master clock mode, the reference clock of the
PLL is provided by OSC and the frequency is 14.31818 MHz.
In slave clock mode, the reference clock is from the XCLK
pin.
Master/Slave Clock Mode
Both VT1621 and VT1621M can be configured either as
master or slave clock mode.
VT1621 and VT1621M provide the pixel clock signal to the
video source and expect incoming data to be available when
required. In slave clock mode, the VT1621 and VT1621M
accept the external pixel clock from the video source.
Revision 1.0 June 17, 2002
We Connect
We Connect
We Connect
We Connect
Device
Source
Video
Source
Device
Video
Configuration 1
Configuration 3
8/12 data
8/12 data
PCLK
XCLK
In master clock mode, the
Hsync
Vsync
PCLK
XCLK
Hsync
Vsync
VT1621M
VT1621M
VT1621
VT1621
Figure 3. Master Clock Mode 1
or
or
- 14-
Master mode
In master clock mode, the VT1621 and VT1621M work as a
master and the video source device works as a slave. The
VT1621 and VT1621M provide a clock signal through the
PCLK pin to the video source device and the video source
device will use this clock as a frequency reference. Then the
video source will generate a clock signal into the XCLK pin.
The VT1621 and VT1621M will use this clock signal to latch
incoming data. The PCLK clock signal can also be used as the
input clock signal connected directly to the XCLK pin. The
HSYNC and VSYNC signals can be programmed to be either
input or output to the TV Encoder. The master clock mode
can be configured as mode 1 and mode 2 illustrated in Figure 3
and Figure 4.
Slave Mode
In slave clock mode, the VT1621 and VT1621M work as a
slave and the video source device works as a master. The
video source device will generate a clock signal input to the
XCLK pin. Through the XCLK pin, the TV Encoder receives
a clock from the video source device and uses this clock to
latch incoming data. Moreover, this clock will be a reference
clock of the VT1621 or the VT1621M for generating a pixel
clock. The HSYNC and VSYNC signals can be programmed
to be either input or output to the VT1621 and VT1621M. In
slave clock mode, both VT1621 and VT1621M can be
configured as illustrated in Figure 5.
Device
Source
Video
Source
Device
Video
Configuration 4
Configuration 2
VT1621 / VT1621M TV Encoder
8/12 data
8/12 data
Hsync
XCLK
XCLK
Hsync
Vsync
Vsync
PCLK
PCLK
VT1621M
VT1621M
VT1621
VT1621
or
or
Funcitonal Descriptions