VT1621M VIA, VT1621M Datasheet - Page 37

• Manufacturer Part Number: VT1621M
• Description: TV Encoder
• Manufacturer: VIA

Clock Frequency
A crystal must be present between the XI and XO pins for
generating a 14.31818 MHz reference clock for the PLL
(Phase Lock Loop). In master clock mode, the PLL uses this
clock as a reference. In slave mode, the PLL uses the clock
from the XCLK pin as a reference clock. The PLL generates
2 clocks: One is pixel clock output on the PCLK pin (for
master mode use only) and the other is the pixel clock used
by the Scaler and Encoder engines.
calculated by the following formula:
The settings of the PLL control registers are listed in Table 3
on page 6.
Revision 1.0 June 17, 2002
F
We Connect
We Connect
We Connect
We Connect
clk
= F
RefClk
* N / (D*P)
The frequency is
- 32-
Mode
24*
25*
27*
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
1
2
3
4
6
7
8
9
Pixel(MHz)
VT1621 / VT1621M TV Encoder
21.000000
26.250000
20.139860
24.671329
28.125000
23.790210
29.454545
25.000000
31.500000
21.146853
26.433566
30.209790
24.000000
26.250000
31.500000
24.671329
28.195804
30.209790
29.500000
36.000000
39.272727
43.636364
47.832169
13.500000
13.500000
14.318180
Table 7. Clock Settings
14.5
2.5
3.5
2.5
2.5
2.5
3.5
2.5
6.5
6.5
3.5
2.5
6.5
6.5
2.5
3.5
3.5
6.5
2.5
2.5
D
2
4
2
3
2
2
Functional Descriptions
128
239
152
44
44
64
56
55
54
36
55
44
48
96
96
88
44
44
56
96
44
48
32
33
33
28
N
12
12
13
13
13
10
13
15
10
13
10
14
14
14
P
7
7
9
8
7
8
7
8
7
5
3
7