VT6516 ETC, VT6516 Datasheet - Page 16

• Manufacturer Part Number: VT6516
• Description: 16/12 PORT 10/1000 ASE T/TX
• Manufacturer: ETC

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MII Interface
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Table
Table
Table
Table
Table
Table
Table
VIA Technologies, Inc.
HA[2:0]
HD[15:0]
HCS
IOR
IOW
INTRQ
TCLK[11:0]
I/O
O
I
I
I
I
I
HOST IDE-Interface Address Bus:
3’b000: command the switch that the whole 16-bit data in the HOST data
3’b001: command the switch that only the 8-bit data in the HOST data bus
3’b010: command the switch to write the low byte in the HOST data bus
3’b011: command the switch to write the low byte in the HOST data bus
3’b1xx: bus-idle command. Keep this address bus to be 3’b111 as the
HOST IDE-Interface Data Bus:
The whole 16-bit data bus is valid for packet data read/write. However,
only the 8-bit data bus is valid for internal registers read/write.
HOST Chip Select:
Active LOW.
interface.
IO READ:
High-to-Low Edge Trigger.
begin the read cycle of HOST IDE interface.
IO READ:
High-to-Low Edge Trigger.
begin the write cycle of HOST IDE interface.
Interrupt Request:
Connected to the HOST external interrupt pin. It is asserted as the
following four interrupt events happen:
(1) MII Management Registers read/write command done
(2) EEPROM read/write command done
(3) Receiving a packet destined to HOST
(4) Finishing transmission of a packet issued by HOST
The interrupt cause is recorded in register IRQSTS[3:0] in address 2000H.
To clear the individual interrupt, The corresponding register has to be
written:
(1) register CLR_PHY_INT in 1806H for PHY interrupt.
(2) register CLR_EE_INT in 1C04H for EEPROM interrupt.
(3) register CLR_RCV_INT in 6403H for packet-receiving interrupt.
l
Transmit Clock for Port 0-11:
TCLK is driven by the PHY device. TCLK is a continuous clock that
provides the timing reference for the transfer of the TXEN and TXD
signals to the PHY. A PHY operating at 100Mbps must provide a TCLK
frequency of 25MHz and a PHY operating at 10Mbps must provide a
TCLK frequency of 2.5MHz.
register CLR_SENT_INT in 6411H for packet-sent interrupt.
bus HD[15:0] is valid for packet-data read/write.
HD[15:0] is valid for internal registers read/write.
HD[15:0] into the low byte of the 16-bit switch address register
for internal registers reference.
HD[15:0] into the high byte of the 16-bit switch address register
for internal registers reference.
HOST has no access to VT-3061A.
-16-
HCS
must be asserted during the access of HOST IDE
Preliminary VT6516 Datarsheet
IOR
IOW
must be asserted from high to low to
must be asserted from high to low to