SM55161A Austin Semiconductor, SM55161A Datasheet - Page 17

• Manufacturer Part Number: SM55161A
• Description: 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM
• Manufacturer: Austin Semiconductor

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block write (continued)
along one row. Block 0 comprises columns 0 –7,
block 1 comprises columns 7 –15, block 2 comprises columns 16
–23, etc., as shown in Figure 11.
column addresses (A3–A8) are latched on the first falling edge
of CASx to decode one of the 64 blocks. Address bits A0–A2
are ignored. Each 2M-bit half has the same block selected.
write cycle except DSF is held high on the first falling edge of
CASx\. As in a DRAM write operation, CASL\ and CASU\
enable the corresponding lower and upper DRAM DQ bytes to
be written. The column-mask data is input via the DQs and is
latched on either the first falling edge of CASx\ or the falling
edge of WE\, whichever occurs later. The 16-bit color-data
register must be loaded prior to performing a block write as
described below. Refer to the write-per-bit section for details on
use of the write-mask capability, allowing additional performance
options.
Example of block write:
Block-write column address = 110000000
Column-mask register =
FIGURE 11: Block Columns Organization
SMJ55161A
Rev. 1.6 03/05
Write-mask register =
Color-data register =
A set of eight columns makes a block, resulting in 64 blocks
During block-write cycles, only the six most significant
A block-write cycle is entered in a manner similar to a DRAM
Austin Semiconductor, Inc.
bit 0
1011
1110
1111
Quad
1st
(A0–A8 from left to right)
1011
1111
0000
Quad
2nd
1100
1111
0111
Quad
3rd
1011
1010
Quad
0111
4th
bit 15
17
Column-address bits A0 and A2 are ignored. Block 0 (columns
0 –7) is selected for each 2M-bit half. The first half has
DQ0–DQ2 written with bits 0–2 from the color-data register
(101) to first four columns of block 0. DQ3 is not written and
retains its previous data due to write-mask-register-bit 3
being 0. DQ4–DQ7 has all four columns masked off due to
column-mask bits 4–7 being 0 so that no data is written.
with bits 8 –11 from the color-data register (1100) to columns
1–3 of its block 0. Column 0 is not written and retains its previ-
ous data on all four DQs due to column-mask-register-bit 8
being 0.
12, 14, and 15 from the color-data register to column 0 and
column 2 of its block 0. DQ13 retains its previous data on all
columns due to the write mask. Columns 1 and 3 retain their
previous data on all DQs due to the column mask. If the previ-
ous data for DQ12-DQ15 is all 0s, the upper half (DQ12-DQ15)
contains the data pattern shown in Figure 12 after the block-
write operation shown in the previous example.
FIGURE 12:
DQ12-DQ15 After A Block-Write
Operation With Previous Data Of 0
The second half (DQ8–DQ11 ) has its four DQs written
DQ12–DQ15 has DQ12, DQ14, and DQ15 written with bits
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Example of Upper
Production
SM55161A
VRAM