SM5838AS Nippon Precision Circuits Inc, SM5838AS Datasheet - Page 7

• Manufacturer Part Number: SM5838AS
• Description: 5120 X 8-bit Synchronous FIFO
• Manufacturer: Nippon Precision Circuits Inc

Write Cycle
The input data address is determined by the write
address pointer position. The write address pointer is
reset by RW (write reset cycle), and is incremented
on the rising edge of CLK whenever WE is LOW.
Read Cycle
The output data address is determined by the read
address pointer position. The read address pointer is
reset by RR (read reset cycle), and is incremented on
the rising edge of CLK whenever RE is LOW. Data
output starts t
the start of the read cycle and continues until t
(min) after the next rising edge of CLK.
DOUT
CLK
DIN
WE
CLK
RE
(n-1)
(n-1)
A
(max) after the rising edge of CLK at
t
CKW
t
CKW
t
A
n cycle
n cycle
t
CKW
t
t
(n)
CKW
DS
(n)
t
t
DH
t
WEH
OH
t
t
REH
A
n+1 cycle
n+1 cycle
t
WES
t
SM5838AS
(n+1)
OH
t
DS
RES
(n+1)
Data input occurs on the rising edge of CLK at the
end of the write cycle.
When WE goes HIGH, write operation is disabled
and the write address pointer stops.
When RE goes HIGH, read operation is disabled and
the read address pointer stops.
Note that data being read was written at least 20
write cycles previously (FIFO minimum delay).
Therefore, if (write address pointer)
pointer) = 1 to 19, then a possibility exists that data
from the preceding line is output instead.
t
t
DH
WEH
t
disable cycle
REH
disable cycle
t
WES
t
RES
RR="H" , OE="L"
RW="H"
NIPPON PRECISION CIRCUITS—7
t
t
OH
A
n+2 cycle
n+2 cycle
(n+2)
(n+2)
(read address