SM5838AS Nippon Precision Circuits Inc, SM5838AS Datasheet - Page 8

• Manufacturer Part Number: SM5838AS
• Description: 5120 X 8-bit Synchronous FIFO
• Manufacturer: Nippon Precision Circuits Inc

Output Enable
When OE is HIGH, DOUT0 to DOUT7 become high
impedance. Note that because RE operation is inde-
pendent of OE operation, the read address pointer
can be incremented even when the outputs are high
impedance.
TYPICAL APPLICATIONS
Note that at power-ON, the write address pointer and
read address pointer positions are undefined.
Accordingly, RW and RR reset cycles are required.
1H Delay Line
A 5120-word delay line can be realized by perform-
ing simultaneous write reset and read reset at power-
ON.
An n-word delay line (21 to 5210-word) can be real-
ized using any of the following methods.
1H (5120-word) delay line timing
DOUT
DOUT
DIN
CLK
RW
RR
CLK
OE
(n-1)
t
RS
t
t
t
RH
0 cycle
CKW
OEH
t
A
n cycle
t
DS
0
t
DH
1 cycle
t
t
CKW
OES
(n)
1
5120 cycle
2 cycle
1H
t
OZ
2
n+1 cycle
SM5838AS
5118
5119
cycle
Hi-Z
1. Perform reset in sync with desired delay length.
2. Stagger RW and RR timing to desired delay
3. Manipulate the write or read address pointer
5119
t
OEH
length.
using WE or RE to disable incrementing to
maintain sync with desired delay length.
n+2 cycle
5120+0
t
A
cycle
0
0
t
t
OES
OH
5120+1
cycle
RR="H" ,RE="L"
NIPPON PRECISION CIRCUITS—8
1
1
t
ZO
5120+2
t
2H
cycle
WE="L" , RE="L" , OE="L"
A
n+3 cycle
2
2
5120+3
cycle
(n+3)
3
3