SM5956A NPC, SM5956A Datasheet - Page 14

• Manufacturer Part Number: SM5956A
• Description: 6-channel Asynchronous Sample Rate Converter
• Manufacturer: NPC

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System Reset (ERROR, RSTN pins)
Under the following conditions, the system must be reset for normal conversion operation. Reset occurs using
a LOW-level pulse input on the RSTN pin.
I
I
I
I
I
I
Output frequency [kHz]
When power is applied
The reset should be released (RSTN = L → H) after the supply voltage and LRCI, BCKI, SCK (and LRCO,
BCKO in slave mode) clocks have stabilized.
When the SCK clock is not continuous
A reset is required when the SCK clock is dynamically switched or is not continuous, such as when switch-
ing the sampling frequency or when the clock momentarily stops due to the state of another IC. The reset
should be released (RSTN = L → H) after the SCK clock has stabilized.
When the LRCI, BCKI inputs are not continuous (SELFN = H)
A reset is required when the LRCI and BCKI clocks are dynamically switched or are not continuous, such as
when switching the sampling frequency or when the clock momentarily stops due to the state of another IC.
The ERROR pin goes L → H to indicate the presence of an input problem, but the LSI continues to operate.
The output generated as a result of the non-continuous clocks is not guaranteed, and it is recommended that
the outputs be muted externally using DMUTEN or other means. The reset should be released (RSTN = L →
H) after the LRCI and BCKI clocks have stabilized.
When the LRCO, BCKO inputs (in slave mode) are not continuous (SELFN = H)
A reset is required when the LRCO and BCKO clocks are dynamically switched or are not continuous, such
as when switching the sampling frequency or when the clock momentarily stops due to the state of another
IC. The ERROR pin goes L → H to indicate the presence of a slave input problem, but the LSI continues to
operate. The output generated as a result of the non-continuous clocks is not guaranteed, and it is recom-
mended that the outputs be muted externally using DMUTEN or other means. The reset should be released
(RSTN = L → H) after the LRCO and BCKO clocks have stabilized.
A reset is required, in such cases where the error is generated, when the input/output sample rate conversion
ratio is set to an incorrect value based on the non-continuous clock, resulting in incorrect output data.
Output state during the reset interval
The DOA, DOB, DOC, and DITO are tied LOW (See “Direct Mute” for operation after reset is released). In
master mode, the LRCO and BCKO pins are also tied LOW.
The required time to detect ERROR
The ERROR detection block counts input-clock and output-clock for a given times (SLAVEN = L). ERROR
pin changes HIGH-level when the observed counts does not agree with the expected counts. Therefore it
needs some time for ERROR to reflect a condition of the clock (see table below). In the case of SELFN = L,
the same time is required to change H → L.
44.1
32
48
The ERROR by LRCI, BCKI stopping
min [ms]
6.0
4.3
4.0
max [ms]
SM5956A
8.0
5.8
5.3
The ERROR by LRCO, BCKO stopping
min [µs]
93.8
68.0
62.5
SEIKO NPC CORPORATION —14
max [µs]
125.0
90.7
83.3