ST7576 Sitronix Technology, ST7576 Datasheet - Page 15
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ST7576
Manufacturer Part Number
ST7576
Description
Dot Matrix LCD Controller/Driver
Manufacturer
Sitronix Technology
Datasheet
1.ST7576.pdf
(54 pages)
ST7576
Ver 1.0
D3 to D2
D7 to D6
D5 to D4(X)
D1
D7(SCLK)
D0
D6(SDA)
D4(CSB)
D3 to D0
D5(A0)
RWR
ERD
(SDA_IN)
(SCLK)
(SDA_OUT)
(SA)
I/O
I
I
Read/Write execution control pin (PS[0:1]=[L:H])
When in the serial interface must fix to ”H”
Read/Write execution control pin (PS[0:1]=[L:H])
When in the serial interface must fix to ” H”
When using 8-bit parallel interface : 6800 . 8080
8-bit bi-directional data bus that is connected to the standard 8-bit
microprocessor data bus.
When chip select is not active, D0 to D7 is high impedance.
When using serial interface: 4-LINE.3-LINE
D7: serial input clock (SCLK) ; D6: serial input data (SDA)
D5: command/data selection (A0) ; D4: chip select pin(CSB)
D3,D2.D1.D0: must fix to ” H”
When using 3-line A0 must fix to “H”
When using I
D7: serial clock input (SCLK)
D6: serial input data (SDA_IN)
D3, D2: (SDA_OUT) serial data acknowledge for the I
connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully
I
from the serial data line is advantageous in chip on glass (COG)
applications. In COG application where the track resistance from the
SDA_OUT pad to the system SDA line can be significant, a potential
divider is generated by the bus pull-up resistor and the ITO track
resistance. It is possible the during the acknowledge cycle the ST7576
will not be able to create a valid logic 0 level. By splitting the SDA_IN
input from the SDA_OUT output the device could be used in a mode
that ignores the acknowledge bit. In COG applications where the
acknowledge cycle is required, it is necessary to minimize the track
resistance from the SDA_OUT pad to the system SDA line to guarantee
a valid low level.
D6, D3,D2 must be connected together (SDA)
D4, D5: must fix to ” H”
D0, D1: Is slave address (SA0,SA1), must fix to “H” or “L”
Chip select input pins “CSB” not used must fix to “H”
2
C interface compatible. Having the acknowledge output separated
PS2
PS2
H
L
H
L
6800-series
8080-series
6800-series
8080-series
MPU type
MPU Type
2
C interface
15/54
/WR(R/W)
/RD (E)
/RD
R/W
/WR
E
Read/Write control input pin
R/W="H“: When E is "H", D0 to D7
are in an output status.
R/W="L“: The data on D0 to D7 are
latched at the falling edge of the E
signal.
Read enable clock input pin
When /RD is "L", D0 to D7 are in an
output status.
Read/Write control input pin
R/W="H“: read
R/W="L”: write
Write enable clock input pin
The data on D0 to D7 are latched
at the rising edge of the /WR
signal
Description
Description
2
C interface. By
www.DataSheet4U.com
2007/01/29
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