T436416A TM, T436416A Datasheet
T436416A
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T436416A Summary of contents
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... TM Technology Inc. reserves the right to change products or specifications without notice 16bit x 4Banks Synchronous DRAM GRNERAL DESCRIPTION The T436416A is 67,108,864 bits synchronous high data rate Dynamic RAM organized 1,048,576 words by 16 bits , fabricated with high performance CMOS technology . Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clockcycle ...
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... D ata Input R egister olum n D ecoder Latency & Burst Length Program m ing R egister Tim ing Register T436416A L(U)D QM Publication Date: MAY. 2003 Revision ...
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... Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device T436416A WE , active. Publication Date: MAY. 2003 Revision: B ...
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... CLK C ADD C OUT Value -1.0 to 4.6 -1 +70 -55 to +125 Typ Max. Unit 3.3 3.6 V 3.0 V + Min Max 2.5 4.0 2.5 5.0 4.0 6.5 2.5 5.0 Publication Date: MAY. 2003 T436416A Unit Notes =-2mA OH I =2mA Unit Revision: B ...
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... P. 5 T436416A Test Condition Burst Length = (min) , (min), CKE V (max), =15ns ...
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... DC Output Load Circuit TM Technology Inc. reserves the right to change products or specifications without notice Value 3 1 1.4 See Fig.2 VOH(DC)=2.4,IOH=-2mA VOL(DC)=0.4,IOL=2mA P. 6 T436416A Unit Output ZO=50 ohm (Fig.2)AC Output Load Circuit Publication Date: MAY. 2003 Revision: B Vtt=1.4v 50 ohm 30pf ...
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... (min) RAS t (max) RAS (min (min) CDL t (min) RDL t (min) BDL t (min) CCD CAS latency=3 CAS latency T436416A Unit -7 100K CLK 2 CLK 1 ...
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... SAC - 2.5 2 2.5 2 2.5 2 1.5 1.75 1. SLZ - 5 SHZ - P.8 T436416A -7.5 -8 -10 Unit Note Max Min Max Min Max 2 Publication Date: MAY. 2003 ...
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... CAS Frequency Latency 100MHz(10.0ns) 2 83MHz(12.0ns) 2 75MHz(13.0ns) 2 66MHz(15.0ns) 2 60MHz(16.7ns Note : 1. 16.7ns is recommended for T436416A RDL 2. Clock count formula : clock TM Technology Inc. reserves the right to change products or specifications without notice RAS RP RRD 60ns 42ns 18ns ...
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... Use in future Vender Specific Mode Register Set Burst length Wrap type Latency mode P.10 T436416A v = Valid x = Don’t care Bit2-0 WT=0 WT=1 000 1 1 001 2 2 010 4 4 011 8 8 100 R R 101 R R 110 R ...
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... Cf.) Sequence of 4 & regardless of the order. TM Technology Inc. reserves the right to change products or specifications without notice. Sequential Addressing Sequence (decimal) 0,1 1,0 Sequential Addressing Sequence (decimal) 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 Sequential Addressing Sequence (decimal) 0,1,2,3,4,5,6,7 1,2,3,4,5,6,7,0 2,3,4,5,6,7,0,1 3,4,5,6,7,0,1,2 4,5,6,7,0,1,2,3 5,6,7,0,1,2,3,4 6,7,0,1,2,3,4,5 7,0,1,2,3,4,5,6 P.11 T436416A Interleave Addressing Sequence (Decimal) 0,1 1,0 Interleave Addressing Sequence (Decimal) 0,1,2,3 1,0,3,2 2,3,0,1 3,2,1,0 Interleave Addressing Sequence (Decimal) 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 Publication Date:MAY. 2003 Revision: B ...
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... (V=Valid , X=Don’t Care , H=Logic High , L=logic Low BA0~BA1 : Program keys.(@MRS after the end of burst. RP P.12 T436416A BA / 0,1 A11 Row Address ...
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... Bs Bs *Note3 *Note3 SRC SLZ Read W rite P.13 T436416A *Note2. *Note4 *Note2 *Note3 *Note4 Rb Qc Read Row Active Precharge Publication Date: MAY. 2003 18 19 :Don't care ...
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... X TMemory Technology Inc. reserves the right to change products or specifications without notice. Active & Read/Write Bank A Bnak B Bank C Bnak D Operation precharge 0 Bank A 0 Bank B 1 Bank C 1 Bank D X All Bamks P.14 T436416A /AP in read/wirte command. 10 Publication Date: MAY. 2003 Revision: B ...
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... P.15 T436416A ...
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... after the clock. SHZ t SAC Publication Date: MAY. 2003 T436416A Revision: B ...
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... RDL P.17 T436416A ...
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... Publication Date: MAY. 2003 T436416A Revision: B ...
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... Publication Date: MAY. 2003 T436416A Revision: B ...
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... Publication Date: MAY. 2003 T436416A Revision: B ...
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... Publication Date: MAY. 2003 T436416A ...
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... Publication Date: MAY. 2003 T436416A Revision: B ...
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... P.23 T436416A ...
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... RDL P. Publication Date: MAY. 2003 T436416A Revision: B ...
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... RAS Publication Date: MAY. 2003 T436416A ...
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... Row active command tiv Publication Date: MAY. 2003 T436416A Revision: B ...
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... P.27 T436416A ...
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... Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. TM Technology Inc. reserves the right to change products or specifications without notice. Auto Refresh Cycle i fre sh P.28 T436416A ...
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... Dimension in inch Max Min Nom Max 1 0.047 0.6 0.016 0.020 0.024 - 0.006 0.40 0.009 0.012 0.016 - 0.0315 0.15 0.002 0.004 0.006 22.62 0.871 0.875 0.905 11.96 0.455 0.463 0.471 10.26 0.396 0.400 0.404 P. Publication Date: MAY. 2003 T436416A Revision: B ...