T436416A TM, T436416A Datasheet - Page 3

• Manufacturer Part Number: T436416A
• Description: 4M X 16 SDRAM
• Manufacturer: TM

PIN DESCRIPTION
TM Technology Inc. reserves the right
to change products or specifications without notice.
DQ0 ~ DQ15
BA0 ~ BA1
V
L(U)DQM
A0 ~ A11
N.C/RFU
V
DDQ
DD
CLK
CKE
CAS
RAS
PIN
WE
CS
/V
/V
SS
SSQ
CH
TE
Column Address Strobe
Power Supply/Ground
Connection/Reserved
Bank Select Address
Row Address Strobe
Data Input/Output
Data Input/Output
Power/Ground
for Future Use
System Clock
Clock Enable
Write Enable
Data Output
Chip Select
Address
NAME
Mask
No
Active on the positive going edge to sample all input.
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11,column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK
with
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK
with CAS low.
Enables column access .
Enables write operation and row precharge.
Latches data in starting from
Makes data output Hi-Z,
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
RAS
low.
P. 3
t
INPUT FUNCTION
SHZ
CAS
after the clock and masks the output.
,
WE
Publication Date: MAY. 2003
active.
T436416A
Revision: B