ST16C552 Exar Corporation, ST16C552 Datasheet - Page 21

• Manufacturer Part Number: ST16C552
• Description: DUAL UART WITH 16-BYTE FIFO AND PARALLEL PRINTER PORT
• Manufacturer: Exar Corporation

ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
ISR BIT 1-3: (logic 0 or cleared is the default condition)
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, and 3 (See Interrupt
Source Table).
ISR BIT 4-5: (logic 0 or cleared is the default condition)
Not Used - initialized to a logic 0.
ISR BIT 6-7: (logic 0 or cleared is the default condition)
These bits are set to a logic 0 when the FIFO’s are not
being used in the 16C450 mode. They are set to a logic
1 when the FIFO’s are enabled in the 16C552/552A
mode.
Line Control Register (LCR)
The Line Control Register is used to specify the
asynchronous data communication format. The word
length, the number of stop bits, and the parity are
selected by writing the appropriate bits in this register.
LCR BIT 0-1: (logic 0 or cleared is the default condi-
tion)
These two bits specify the word length to be transmit-
ted or received.
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in
conjunction with the programmed word length.
Rev. 3.40
BIT-1
0
0
1
1
BIT-0
0
1
0
1
Word length
5
6
7
8
21
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity. (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, receiver checks the data and parity for transmis-
sion errors.
LCR BIT-4:
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted data. The
receiver must be programmed to check the same
format. (normal default condition)
Logic 1 = EVEN Parity is generated by forcing an even
the number of logic 1’s in the transmitted. The receiver
must be programmed to check the same format.
LCR BIT-5:
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
LCR BIT-5 = logic 0, parity is not forced. (normal
default condition)
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit
is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit
is forced to a logical 0 for the transmit and receive
data.
BIT-2
0
1
1
ST16C552/552A
Word length
5,6,7,8
6,7,8
5
(Bit time(s))
Stop bit
length
1-1/2
1
2