STA323W ST Microelectronics, STA323W Datasheet - Page 16

• Manufacturer Part Number: STA323W
• Description: 2.1 High Efficiency Digital Audio System
• Manufacturer: ST Microelectronics

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STA323W
Figure 13.
7.3.1 Delay Serial Clock Enable
7.3.2 Channel Input Mapping
Each channel received via I2S can be mapped to any internal processing channel via the Channel Input
Mapping registers. This allows for flexibility in processing. The default settings of these registers map
each I2S input channel to its corresponding processing channel.
7.4 CONFIGURATION REGISTER C (Address 02h)
7.4.1 DDX
The DDX® Power Output Mode selects how the DDX® output timing is configured. Different power de-
vices can use different output modes. The DDX-2060/2100/2160 recommended use is OM = 10. When
OM=11 the CSZ bits determine the size of the DDX® compensating pulse.
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BIT
BIT
1...0
5
6
7
BIT
D7
4
U
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R/W
R/W
R/W
R/W
R/W
®
Power Output Mode
R/W
R/W
CSZ4
D6
1
LRCKI
BICKI
RST
RST
0
0
1
SDI
RST
10
CSZ3
D5
0
T2
DSCKE
NAME
NAME
C1IM
C2IM
OM (1...0)
NAME
CSZ2
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D4
0
T4
T3
Delay Serial Clock Enable:
0 – No serial clock delay
1 – Serial clock delay by 1 core clock cycle to tolerate
anomalies in some I
0 – Processing channel 1 receives Left I
1 – Processing channel 1 receives Right I
0 – Processing channel 2 receives Left I
1 – Processing channel 2 receives Right I
DDX Power Output Mode:
Selects configuration of DDX
T5
CSZ1
D3
0
T0
2
S master devices
CSZ0
DESCRIPTION
DESCRIPTION
DESCRIPTION
D2
0
T1
®
output.
OM1
D1
2
2
1
S Input
S Input
2
2
S Input
S Input
OM0
D0
0
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