SC26C562 Philips Semiconductors, SC26C562 Datasheet - Page 6

• Manufacturer Part Number: SC26C562
• Description: CMOS dual universal serial communications controller CDUSCC
• Manufacturer: Philips Semiconductors

Philips Semiconductors
PIN DESCRIPTION
1998 Sep 04
A1–A6
D0–D7
RDN
WRN
CSN
RDYN
IRQN
IACKN
X1/CLK
X2
RESETN
RxDA, RxDB
TxDA, TxDB
RTxCA, RTxCB
TRxCA, TRxCB
CMOS dual universal serial communications controller
(CDUSCC)
MNEMONIC
MNEMONIC
31-28,
37, 12
36, 13
39, 10
47-45
21-18
40, 9
DIP
4-2,
22
26
25
43
42
23
7
6
1
PIN NO.
33-30,
40, 14
39, 15
44, 10
PLCC
43, 11
51-49
23-20
4-2,
24
28
27
47
46
25
8
6
1
TYPE
TYPE
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
I
between pins X1 and X2. If a crystal is not used, an external clock is supplied at this input.
Address Lines: Active-high. Address inputs which specify which of the internal registers
is accessed for read/write operation.
Bidirectional Data Bus: Active-high, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All
data, command and status transfers between the CPU and the CDUSCC take place over
this bus. The data bus is enabled when CSN and RDN, or CSN and WRRN are low during
interrupt acknowledge cycles and single address DMA acknowledge cycles.
Read Strobe: Active-low input. When active and CSN is also active, causes the content
of the addressed register to be present on the data bus. RDN is ignored unless CSN is
active.
Write Strobe: Active-low input. When active and CSN is also active, the content of the
data bus is loaded into the addressed register. The transfer occurs on the rising edge of
WRN. WRN is ignored unless CEN is active.
Chip Select: Active-low input. When active, data transfers between the CPU and the
CDUSCC are enabled on D0–D7 as controlled by RDN or WRN and A1–A6 inputs. When
CSN is high, the data lines are placed in the 3-State condition (except during interrupt
acknowledge cycles and single address DMA transfers).
Ready: Active-low, open drain. Used to synchronize data transfers between the CPU and
the CDUSCC. It is valid only during read and write cycles where the CDUSCC is
configured in ‘wait on Rx’, ‘wait on Tx’ or ‘wait on Tx or Rx’ modes, otherwise it is always
inactive. RDYN becomes active on the leading edge of RDN and WRN if the requested
operation cannot be performed (viz, no data in RxFIFO in the case of a read or no room in
the TxFIFO in the case of a write).
Interrupt Request: Active-low, open-drain. This output is asserted upon occurrence of
any enabled interrupting condition. The CPU can read the general status register to
determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle
to cause the CDUSCC to output an interrupt vector on the data bus.
Interrupt Acknowledge: Active-low. When IACKN is asserted, the CDUSCC responds
by either forcing the bus into high-impedance, placing a vector number, call instruction or
zero on the data bus. The vector number can be modified or unmodified by the status. If
no interrupt is pending, IACKN is ignored and the data bus placed in high-impedance.
Crystal or External Clock: When using the crystal oscillator, the crystal is connected
This clock is used to drive the internal bit rate generator, as an optional input to the
counter/timer or DPLL, and to provide other required clocking signals. When a crystal is
used, a capacitor must be connected from this pin to ground.
Crystal 2: Connection for other side of crystal. When a crystal is used, a capacitor must
be connected from this pin to ground. If an external clock is used on X1, this pin should be
left floating.
Master Reset: Active-low. A low on this pin resets the transmitters and receivers and
resets the registers shown in Table 1 of the CDUSCC Users’ Guide. Reset is
asynchronous, i.e., no clock is required.
Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If
external receiver clock is specified for the channel, the input is sampled on the rising edge
of the clock.
Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted
first. This output is in the marking (high) condition when the transmitter is disabled or when
the channel is operating in local loopback mode. If external transmitter clock is specified
for the channel, the data is shifted on the falling edge of the clock.
Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to
supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply
the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock
(1X).
Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver,
transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X),
the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system
clock (X1
2).
6
NAME AND FUNCTION
NAME AND FUNCTION
SC26C562
Product specification