SC26C562 Philips Semiconductors, SC26C562 Datasheet - Page 7

• Manufacturer Part Number: SC26C562
• Description: CMOS dual universal serial communications controller CDUSCC
• Manufacturer: Philips Semiconductors

Philips Semiconductors
PIN DESCRIPTION (Continued)
1998 Sep 04
CTSA/BN,
LCA/BN
DCDA/BN,
SYNIA/BN
RTxDRQA/BN,
GPO1A/BN
TxDRQA/BN,
GPO2A/BN,
RTSA/BN
RTxDAKA/BN,
GPI1A/BN
TxDAKA/BN,
GPI2A/BN
EOPN
RTSA/BN,
SYNOUTA/BN
V
GND
CC
CMOS dual universal serial communications controller
(CDUSCC)
MNEMONIC
MNEMONIC
32, 17
38, 11
34, 15
33, 16
35, 14
44, 5
41, 8
DIP
27
48
24
PIN NO.
26, 13,
35, 19
42, 12
37, 17
36, 18
38, 16
34, 52
PLCC
48, 5
45, 9
41, 7
29
TYPE
TYPE
I/O
I/O
O
O
O
I
I
I
I
I
Channel A (B) Clear-to-Send Input or Loop Control Output: Active-low. The signal
can be programmed to act as an enable for the transmitter when not in loop mode. The
CDUSCC detects logic level transitions on this input and can be programmed to generate
an interrupt when a transition occurs. When operating in the BOP loop mode, this pin be-
comes a loop control output which is asserted and negated by CDUSCC commands. This
output provides the means of controlling external loop interface hardware to go on-line and
off-line without disturbing operation of the loop.
Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-low input, it acts as an enable for the receiver or can be
used as a general purpose input. For the DCD function, the CDUSCC detects logic level
transitions on this pin and can be programmed to generate an interrupt when a transition
occurs. As an active-low external sync input, it is used in COP mode to obtain character
synchronization for the receiver without receipt of a SYN character. This mode can be
used in disc or tape controller applications or for the optional byte timing lead in X.21.
Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose
Output: Active-low. For half-duplex DMA operation, this output indicates to the DMA
controller that one or more characters are available in the receiver FIFO (when the
receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled).
For full-duplex DMA operation, this output indicates to the DMA controller that data is
available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that
can be asserted and negated under program control.
Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send: Active-low. For full-duplex DMA operation, this output indicates to the
DMA controller that the transmit FIFO is not full and can accept more data. When not in
full-duplex DMA mode, this pin can be programmed as a general purpose or a
Request-to-Send output, which can be asserted and negated under program control.
Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input:
Active-low. For half-duplex single address operation, this input indicates to the CDUSCC
that the DMA controller has acquired the bus and that the requested bus cycle (read
receiver FIFO when the receiver is enabled or load transmitter FIFO when the transmitter
is enabled) is beginning. For full-duplex single address DMA operation, this input indicates
to the CDUSCC that the DMA controller has acquired the bus and that the requested read
receiver FIFO bus cycle is beginning. Because the state of this input can be read under
program control, it can be used as a general purpose input when not in single address
DMA mode.
Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-low.
When the channel is programmed for full-duplex single address DMA operation, this input
is asserted to indicate to the CDUSCC that the DMA controller has acquired the bus and
that the requested load transmitter FIFO bus cycle is beginning. Because the state of this
input can be read under program control, it can be used as a general purpose input when
not in full-duplex single address DMA mode.
Done (EOP): Active-low, open-drain. EOPN can be used and is active in both DMA and
non-DMA modes. As an input, EOPN indicates the last DMA transfer cycle to the TxFIFO.
As an output, EOPN indicates either the last DMA transfer from the RxFIFO or that the
transmitted character count has reached terminal count.
Channel A (B) Sync Detect or Request-to-Send: Active-low. If programmed as a sync
output, it is asserted one bit time after the specified sync character (COP or BISYNC
modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send
modem control signal, it functions as described previously for the TxDRQN/RTSN pin.
+5V Power Input
Signal and Power Ground Input
7
NAME AND FUNCTION
NAME AND FUNCTION
SC26C562
Product specification