SC26L198 Philips Semiconductors, SC26L198 Datasheet - Page 24

• Manufacturer Part Number: SC26L198
• Description: Octal UART with TTL compatibility at 3.3V and 5V supply voltages
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 22. XISR – Xon–Xoff Interrupt Status Register
XISR[7:6] – Received X Character Status. This field can be read to
determine if the receiver has encountered an Xon or Xoff character
in the incoming data stream. These bits are maintained until a read
of the XISR. The field is updated by X character reception
regardless of the state of MR0(7, 3:2) or IMR(4). The field can
therefore be used as a character detector for the bit patterns stored
in the Xon and Xoff Character Registers.
XISR[5:4] – Automatic transmission Status. This field indicates the
last flow control character sent in the Auto Receiver flow control
mode. If Auto Receiver mode has not been enabled, this field will
always read b’00. It will likewise reset to b’00 if MR0(3) is reset. If
the Auto Receiver mode is exited while this field reads b’10, it is the
user’s responsibility to transmit an Xon, when appropriate.
XISR[3:2] – TxD flow Status. This field tracks the transmitter’s flow
status as follows:
XISR[1:0] – TxD character Status. This field allows determination of
the type of character being transmitted. If XISR(1:0) is b’01, the
channel is waiting for a data character to transfer from the TxFIFO.
This condition will only occur for a bit time after an Xon or Xoff
character transmission unless the TxFIFO is empty.
Table 26. BRGTCR – BRG Timer Control Register (BRGTCR)
Start/Stop control and clock select register for the two BRG
counters. The clock selection is for the input to the counters. It is
that clock divided by the number represented by the BRGTU and
BRGTL the will be used as the 16x clock for the receivers and
transmitters. When the BRG timer Clock is selected for the
Table 27. ICR – Interrupt Control Register
This register provides a single 7 bit field called the interrupt
threshold for use by the interrupt arbiter. The field is interpreted as a
single unsigned integer. The interrupt arbiter will not generate an
external interrupt request, by asserting IRQN, unless the value of
1995 May 1
Received X Character
Status
00 – none
01 – Xoff received
10 – Xon received
11 – both received
0 – Resets the timer register and
1 – Allows the timer register to
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
00 – normal. The flow control is under host control.
01 – TxD halt pending. After the current character finishes the
transmitter will stop. The status will then change to b’00.
10 – re–enabled. The transmitter had been halted and restarted.
It is sending data characters. After a read of the XISR, it will
return to ”normal” status.
11 – disabled. The transmitter is flow controlled.
BRGTCR b, Register control
Reserved. Set to 0
holds it stopped
Bits 7:6
Bit 7
Bit 7
run.
Automatic X Character
transmission status
00 – none
01 – Xon transmitted
10 – Xoff transmitted
11 – Illegal, does not occur
000 – Sclk / 16
001 – Sclk / 32
010 – Sclk/ 64
011 – Sclk / 128
100 – X1
101 – X1 / 2
110 – I/O1b
111 – G
BRGTCR b, Clock selection
IN
Bits 5:4
(1)
Bit 6:4
Upper seven bits of the Arbitration Threshold
359
TxD flow status
00 – normal
01 – TxD halt pending
10 – re–enabled
11 – flow disabled
0 – Resets the timer register and
1 – Allows the timer register to
BRGTCR a, Register control
Table 23. WDTRCR – Watch-dog Timer Enable
This register enables the watch-dog Timer for each of the 8
receivers on the Octal UART.
Table 24. BRGTRU
This is the upper byte of the 16 bit value used by the BRG timer in
generating a baud rate clock
Table 25. BRGTRL
This is the lower byte of the 16 bit value used by the BRG timer in
generating a baud rate clock.
receiver(s) or transmitter(s) the receivers and transmitters will
consider it as a 16x clock and further device it by 16. In other words
the receivers and transmitters will always be in the 16x ode of
operation when the internal BRG timer is selected for their clock.
the highest priority interrupt exceeds the value of the interrupt
threshold. If the highest bidder in the interrupt arbitration is lower
than the threshold level set by the ICR, the Current Interrupt
Register, CIR, will contain x’00. Refer to the functional description of
Bit 7
WDT
1 on
0 off
h
holds it stopped.
Bits 3:2
Bits 6:0
WDT
Bit 6
1 on
0 off
Register
Registers, Upper
Registers, Lower
Bit 3
g
run.
8 MSB of the BRG Timer divisor.
8 LSB of the BRG Timer divisor.
WDT
Bit 5
1 on
0 off
f
SC26C198 SC68C198
–
–
SC26L198 SC68L198
WDT
Bit 4
1 on
0 off
TxD character status
00 – normal TxD data
01 – wait on normal data
10 – Xoff in pending
11 – Xon in pending
e
BRG Timer Reload
BRG Timer Reload
Bits 7:0
Bits 7:0
000 – Sclk / 16
001 – Sclk / 32
010 – Sclk / 64
011 – Sclk / 128
100 – X1
101 – X1 / 2
110 – I/O1a
111 – G
WDT
Bit 3
BRGTCR a, Clock selection
1 on
0 off
d
IN
(0)
Bits 1:0
WDT
Bit 2
1 on
0 off
c
Bit 2:0
Product specification
WDT
Bit 1
1 on
0 off
b
Bit 0
WDT
1 on
0 off
a