SC26L198 Philips Semiconductors, SC26L198 Datasheet - Page 25

• Manufacturer Part Number: SC26L198
• Description: Octal UART with TTL compatibility at 3.3V and 5V supply voltages
• Manufacturer: Philips Semiconductors

Philips Semiconductors
interrupt generation for details on how the various interrupt source
bid values are calculated.
Note: While a watch-dog Timer interrupt is pending, the ICR is not
used and only receiver codes are presented for interrupt arbitration.
This allows receivers with very low count values (perhaps below the
threshold value) to win interrupt arbitration without requiring the user
to explicitly lower the threshold level in the ICR. These bits are the
upper seven (7) bits of the interrupt arbitration system. The lower
three (3) bits represent the channel number.
UCIR – Update CIR
A command based upon a decode of address x’8C. ( UCIR is not a
register!) A write (the write data is not important; a “don’t care”) to
this ’register’ causes the Current Interrupt Register to be updated
with the value that is winning interrupt arbitration. The register
would be used in systems that poll the interrupt status registers
rather than wait for interrupts. Alternatively, the CIR is normally
updated during an Interrupt Acknowledge Bus cycle in interrupt
driven systems.
Table 28. CIR – Current Interrupt Register
The Current Interrupt Register is provided to speed up the
specification of the interrupting condition in the Octal UART. The
CIR is updated at the beginning of an interrupt acknowledge bus
cycle or in response to an Update CIR command. (see immediately
above) Although interrupt arbitration continues in the background,
the current interrupt information remains frozen in the CIR until
another IACKN cycle or Update CIR command occurs. The LSBs of
the CIR provide part of the addressing for various Global Interrupt
registers including the GIBCR, GICR, GITR and the Global RxFIFO
and TxFIFO FIFO. The host CPU need not generate individual
addresses for this information since the interrupt context will remain
stable at the fixed addresses of the Global Interrupt registers until
the CIR is updated. For most interrupting sources, the data
available in the CIR alone will be sufficient to set up a service
routine.
The CIR may be processed as follows:
1995 May 1
Type
00 – other
01 – Transmit
11– Receive w/
errors
10 – Receive w/o
errors
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
Bits 7:6
Current byte count/type
000 – no interrupt
001 – Change of State
010 – Address
Recognition
011 – Xon/Xoff status
100 – Not used
101 – Break change
110, 111 do not occur
Current count code
0 => 9 or less
characters
1 => 10 characters
.
.
5 => 14 characters
6 => 15 characters
7 => 16
(See also GIBCR)
Bits 5:3
Channel number
000 = a
001 = b
010 = c
011 = d
111 = h
000 = a
001 = b
010 = c
011 = d
111 = h
Bits 2:0
360
If CIR[7] = 1, then a receiver interrupt is pending and the count is
CIR[5:3], channel is CIR[2:0]
Else If CIR[6] = 1 then a transmitter interrupt is pending and the
count is CIR[5:3], channel is CIR[2:0]
Else the interrupt is another type, specified in CIR[5:3]
Note: The GIBCR, Global Interrupting Byte Count Register, may be
read to determine an exact character count if 9 or less characters
are indicated in the count field of the CIR.
Table 29. IVR – Interrupt Vector Register
The IVR contains the byte that will be placed on the data bus during
an IACKN cycle when the GCCR bits (2:1) are set to binary ‘01’.
This is the unmodified form of the interrupt vector.
Table 30. Modification of the IVR
The table above indicates how the IVR may be modified by the
interrupting source. The modification of the IVR as it is presented to
the data bus during an IACK cycle is controlled by the setting of the
bits (2:1) in the GCCR (Global Chip Configuration Register)
Table 31. GICR – Global Interrupting Channel
A register associated with the interrupting channel as defined in the
CIR. It contains the interrupting channel code for all interrupts.
Table 32. GIBCR – Global Interrupting Byte Count
A register associated with the interrupting channel as defined in the
CIR. Its numerical value equals
the number of bytes minus 1 (count – 1) ready for transfer to the
transmitter or transfer from the receiver. It is undefined for other
types of interrupts
Always contains
bits (7:5) of the IVR
Reserved
Bits 7:4
Bits 7:5
Reserved
Bits 7:3
Register
Register
8 data bits of the Interrupt Vector (IVR)
Channel byte count code
0000 = 1 AND RxRDY status set for RxFIFO
0000 = 1 AND TxRDY status set for TxD
0001 = 2
0010 = 3
.
1111 = 16
Will be replaced
with current
interrupt type if IVC
field of GCCR > 1
SC26C198 SC68C198
SC26L198 SC68L198
Bits 4:3
Bits 7:0
100 = e
101 = f
110 = g
111 = h
Channel code
Bits 3:0
Bits 2:0
Replaced with
interrupting channel
number if IVC field of
GCCR > 0
Product specification
Bits 2:0
000 = a
001 = b
010 = c
011 = d