SC28L194 Philips Semiconductors, SC28L194 Datasheet - Page 25

• Manufacturer Part Number: SC28L194
• Description: Quad UART for 3.3V and 5V supply voltage
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 22. XISR - Xon-Xoff Interrupt Status Register
See MR0 for a description of enabling these functions
NOTE: Bits of this register may be cleared by a read of the register.
XISR[7:6] - Received X Character Status. This field can be read to
determine if the receiver has encountered an Xon or Xoff character
in the incoming data stream. These bits are maintained until a read
of the XISR. The field is updated by X character reception
regardless of the state of MR0(7, 3:2) or IMR(4). The field can
therefore be used as a character detector for the bit patterns stored
in the Xon and Xoff Character Registers.
XISR[5:4] - Automatic transmission Status. This field indicates the
last flow control character sent in the Auto Receiver flow control
mode. If Auto Receiver mode has not been enabled, this field will
always read b’00. It will likewise reset to b’00 if MR0(3) is reset. If
the Auto Receiver mode is exited while this field reads b’10, it is the
user’s responsibility to transmit an Xon, when appropriate.
XISR[3:2] - TxD flow Status. This field tracks the transmitter’s flow
status as follows:
XISR[1:0] - TxD character Status. This field allows determination of
the type of character being transmitted. If XISR(1:0) is b’01, the
channel is waiting for a data character to transfer from the TxFIFO.
This condition will only occur for a bit time after an Xon or Xoff
character transmission unless the TxFIFO is empty.
1998 Sep 21
Received X Character
Status
00 - none
01 - Xoff received
10 - Xon received
11 - both received
Quad UART for 3.3V and 5V supply voltage
00 - normal. The flow control is under host control.
01 - TxD halt pending. After the current character finishes the
transmitter will stop. The status will then change to b’00.
10 - re-enabled. The transmitter had been halted and restarted. It
is sending data characters. After a read of the XISR, it will return
to “normal” status.
11 - disabled. The transmitter is flow controlled.
Bits 7:6
Automatic X Character
transmission status
00 - none
01 - Xon transmitted
10 - Xoff transmitted
11 - Illegal, does not occur
Bits 5:4
TxD flow status
00 - normal
01 - TxD halt pending
10 - re-enabled
11 - flow disabled
25
Table 23. WDTRCR - Watch-dog Run Control
This register enables the watch-dog Timer for each of the 4
receivers on the Quad UART
Table 24. BRGTRU
This is the upper byte of the 16 bit value used by the BRG timer in
generating a baud rate clock
Table 25. BRGTRL
This is the lower byte of the 16 bit value used by the BRG timer in
generating a baud rate clock.
Reserved
Bits 7:4
Bits 3:2
Register
Registers, Upper (Timers A & B)
Registers, Lower (Timers A & B)
WDT d
8 MSB of the BRG Timer divisor.
Bit 3
8 LSB of the BRG Timer divisor.
1 on
0 off
-
-
TxD character status
00 - normal TxD data
01 - wait on normal data
10 - Xoff in pending
11 - Xon in pending
Bits 7:0
BRG Timer Reload
Bits 7:0
BRG Timer Reload
WDT c
Bit 2
1 on
0 off
Bits 1:0
Preliminary specification
WDT b
Bit 1
1 on
0 off
SC28L194
WDT a
Bit 0
1 on
0 off