SC28L92 Philips Semiconductors, SC28L92 Datasheet
SC28L92
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SC28L92 Summary of contents
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... SC28L92 3.3V–5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART) Product specification Supersedes data of 1999 May 07 IC19 Data Handbook hilips Semiconductors INTEGRATED CIRCUITS 2000 Jan 21 ...
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... These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control. The SC28L92 is available in two package versions: a 44-pin PLCC and 44-pin plastic quad flat pack (PQFP). FEATURES Member of IMPACT family: 3.3 to 5.0 volt , – +85 C and 68K for 80xxx bus interface for all devices ...
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... Philips Semiconductors 3.3V–5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART) ORDERING INFORMATION DESCRIPTION 44-Pin Plastic Leaded Chip Carrier (PLCC) 44-Pin Plastic Quad Flat Pack (PQFP) 2000 Jan 21 INDUSTRIAL V = +3.3 +5V 10 –40 to +85 C DRAWING NUMBER amb SC28L92A1A SC28L92A1B 3 Product specification SC28L92 SOT187–2 SOT307-2 ...
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... IP0 WRN RDN 41 IP3 11 RxDB I/M 43 IP1 13 TxDB OP1 15 OP3 SD00671 4 Product specification SC28L92 PLCC Pin Function Pin Function 16 OP5 31 OP2 17 OP7 32 OP0 TxDA RxDA 21 D7 ...
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... IP0 R/ DACKN 41 IP3 11 RxDB I/M 43 IP1 13 TxDB OP1 15 OP3 SD00673 5 Product specification SC28L92 PLCC Pin Function Pin Function 16 OP5 31 OP2 17 OP7 32 OP0 TxDA RxDA 21 D7 ...
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... CTU 2000 Jan 21 16 BYTE TRANSMIT SHIFT REGISTER 16 BYTE RECEIVE WATCH DOG TIMER RECEIVE SHIFT DETECTORS (4) OUTPUT PORT SELECT LOGIC Figure 1. Block Diagram (80XXX mode) 6 Product specification SC28L92 CHANNEL A TxDA FIFO TRANSMIT FIFO RxDA REGISTER MRA0 CRA SRA TxDB CHANNEL B ...
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... CTU 2000 Jan 21 16 BYTE TRANSMIT SHIFT REGISTER 16 BYTE RECEIVE WATCH DOG TIMER RECEIVE SHIFT DETECTORS (4) OUTPUT PORT SELECT LOGIC Figure 2. Block Diagram (68XXX mode) 7 Product specification SC28L92 CHANNEL A TxDA FIFO TRANSMIT FIFO RxDA REGISTER MRA0 CRA SRA TxDB CHANNEL B ...
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... Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. V Pwr Power Supply: +3.3 or +5V supply input CC GND Pwr Ground 2000 Jan 21 NAME AND FUNCTION 10% 8 Product specification SC28L92 ...
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... Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. V Pwr Power Supply: +3.3 or +5V supply input 10% CC GND Pwr Ground 2000 Jan 21 NAME AND FUNCTION 9 Product specification SC28L92 ...
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... CMOS input levels CMOS input levels . All time measurements are referenced at input voltages of 0.8V and CC when the input pins are -0.2V and Product specification SC28L92 RATING UNIT Note 4 C –65 to +150 C –0.5 to +7.0 V –0 +0 2 ...
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... CMOS input levels CMOS input levels . All time measurements are referenced at input voltages of 0.8V and CC when the input pins are –0.2V and Product specification SC28L92 LIMITS Min Typ Max UNIT 0.65 0.2 0.8*V 1 0.2 0 –0.5 V –0.2 ...
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... Transmitter Timing, external clock (See Figure 12) t TxD output delay from TxC low (TxC input pin) *TXD t Output delay from TxC output pin low to TxD data output *TCS 2000 Jan 21 PARAMETER Product specification SC28L92 4 LIMITS Min Typ Max UNIT 100 ...
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... It is not necessary to wait for DACKN to insure the proper operation of the SC28C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the bus cycle ...
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... Transmitter Timing, external clock (See Figure 12) t TxD output delay from TxC low (TxC input pin) *TXD t Output delay from TxC output pin low to TxD data output *TCS 2000 Jan PARAMETER Product specification SC28L92 4 LIMITS Min Typ Max UNIT 100 ...
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... It is not necessary to wait for DACKN to insure the proper operation of the SC28C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the bus cycle ...
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... Philips Semiconductors 3.3V–5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART) Block Diagram The SC28L92 DUART consists of the following eight major sections: data bus buffer, operation control, interrupt control, timing, communications Channels A and B, input port and output port. Refer to the Block Diagram. Data Bus Buffer The data bus buffer provides the interface between the external and internal data buses ...
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... ISR will return a x’00 character. This action may present the appearance of a spurious interrupt. Communications Channels A and B Each communications channel of the SC28L92 comprises a full-duplex asynchronous receiver/transmitter (UART). The operating frequency for each receiver and transmitter can be selected independently from the baud rate generator, the counter/timer, or from an external input ...
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... DMA control. OPERATION Transmitter The SC28L92 is conditioned to transmit data when the transmitter is enabled through the command register. The SC28L92 indicates to the CPU that it is ready to accept a character by setting the TxRDY bit in the status register. This condition can be programmed to generate an interrupt request at OP6 or OP7 and INTRN ...
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... ISR will show the “Counter Ready” bit not set. If nothing else is interrupting, this read of the ISR will return a x’00 character. Multi-drop Mode (9-bit or Wake-Up) The DUART is equipped with a wake up mode for multi-drop applications. This mode is selected by programming bits 19 Product specification SC28L92 ...
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... FIFO while the A/D bit is loaded into the status FIFO position normally used for parity error (SRA[5] or SRB[5]). Framing error, overrun error, and break detect operate normally whether or not the receive is enabled. Table 1. SC28L92 register addressing READ (RDN = 0), WRITE (WRN = ...
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... Bit 2 Disable Tx Enable Tx Bit 5 Bit 4 Bit 3 Overrun Error TxEMT Bit 5 Bit 4 Bit 3 TxRDTYB Counter Ready Bit 5 Bit 4 Bit 3 TxRDTYB Counter Ready Bits 7:0 8 MSB of the BRG Timer divisor. 21 Product specification SC28L92 IPCR R ACR W ISR R IMR W CTU R CTL R CTPU W CTPL W IPR R OPCR W Bits ...
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... FIFO byte FIFO Table 3a. Receiver FIFO interrupt fill level(MR0(3)=1 (16 bytes) MR0[6] MR1[ Product specification SC28L92 Bit 1 Bit 0 Enable IP1 Enable IP0 Bit 2 Bit 1 Bit 0 State of IP1 State of IP0 Bit 2 Bit 1 Bit 0 State State of IP1 ...
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... This bit selects the parity type (odd or even) if the ‘with parity’ mode is programmed by MR1A[4:3], and the polarity of the forced parity bit if the ‘force parity’ mode is programmed. It has no effect if the ‘no 23 Product specification SC28L92 BIT 2 BIT 1 BIT 0 BITS PER CHARACTER ...
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... Channel A transmit shift register and in the TxFIFO, if any, are completely transmitted including the programmed number of stop bits, if the transmitter is not enabled. 24 Product specification SC28L92 BIT 2 BIT 1 BIT 0 STOP BIT LENGTH 4 = 0.813 8 = 1.563 ...
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... MR1B. Accesses to MR2B do not change the pointer. The bit definitions for mode register are identical to the bit definitions for MR2A, except that all control actions apply to the Channel B receiver and transmitter and the corresponding inputs and outputs. 25 Product specification SC28L92 ...
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... This field selects the baud rate clock for the Channel B transmitter. The field definition is as shown in Table 5, except as follows: 1110 IP5–1X The transmitter clock is always a 16X clock except for CSRB[3:0] = 1111. 26 Product specification SC28L92 CSR (3:0) TRANSMITTER CLOCK SELECT See Text and table 5 MR0[ (Extended Mode II) ACR[ ACR[ 4,800 ...
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... NOTE: Duty cycle of 16X clock is 50% 1% 2000 Jan 21 ACTUAL 16X CLOCK (KHz) 0.8 1.2 1.759 2.153 2.4 3.2 4.8 9.6 16.756 19.2 28.8 32.056 38.4 76.8 115.2 153.6 307.2 614.4 27 Product specification SC28L92 ERROR (%) 0 0 –0.069 0.059 –0.260 0 0 0.175 ...
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... CRA[2]—Enable Channel A Transmitter Enables operation of the Channel A transmitter. The TxRDY and TxEMT status bits will be asserted if the transmitter is idle. 28 Product specification SC28L92 BIT 2 BIT 1 BIT 0 Disable Rx Enable Yes ...
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... SRA[0]—Channel A Receiver Ready (RxRDYA) This bit indicates that a character has been received and is waiting in the FIFO to be read by the CPU set when the character is transferred from the receive shift register to the FIFO and reset 29 Product specification SC28L92 BIT 2 BIT 1 BIT 0 TxRDY FFULL ...
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... If data is not being transmitted, a free running 1X clock is output. 11 The 1X clock for the Channel A receiver, which is the clock that samples the received data. If data is not being received, a free running 1X clock is output. 30 Product specification SC28L92 BIT 2 BIT 1 BIT 0 OP3 OP2 OP1 OP0 ...
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... BIT 5 BIT 4 BIT Pin High 0 = Pin High 0 = Pin High 1 = Pin Low 1 = Pin Low 1 = Pin Low 31 Product specification SC28L92 BIT 2 BIT 1 BIT 1=set bit 1=set bit 1=set bit change change change ...
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... IPCR [3:0]—IP3, IP2, IP1, IP0 Change-of-State These bits provide the current state of the respective inputs. The information is unlatched and reflects the state of the input pins at the time the IPCR is read. 32 Product specification SC28L92 BIT 2 BIT 1 BIT 0 Delta IP3 int Delta IP3 int ...
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... BIT 4 BIT 3 RxRDY/ TxRDY B Counter FFULL B Ready 0 = not 0 = not 0 = not enabled enabled enabled 1 = enabled 1 = enabled 1 = enabled 33 Product specification SC28L92 BIT 2 BIT 1 BIT 0 Delta RxRDY/ TxRDY A Break A FFULL not active 0 = not active 0 = not active 1 = active 1 = active 1 = active BIT 2 BIT 1 BIT 0 Delta ...
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... SC26L92. The contents of this register will be placed on the data bus when IACKN is asserted low or a read of address 0xC is performed. When not operating in the 68XXX mode, this register may be used as a general purpose one byte storage register. A convenient use could be to store a “shadow” of the contents of another SC28L92 register (IMR, for example). CTPU and CTPL – Counter/Timer Registers ...
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... OP0. When OP0 (or OP1) is controlled by the receiver, the meaning of that pin will be. RESETN Figure 4. Reset Timing RWD NOT VALID FLOAT VALID t RWD VALID Figure 5. Bus Timing (80XXX mode) 35 Product specification SC28L92 t RES 68XXX Mode SD00696 SD00087 ...
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... Figure 7. Bus Timing (Write Cycle) (68XXX mode) 2000 Jan 21 t CSC RWD NOT DATA VALID VALID t DCR t DAT t CSC DCW t DAT 36 Product specification SC28L92 DAH SD00687 RWD DAH SD00688 ...
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... IP0–IP6 (a) INPUT PINS WRN OP0–OP7 (b) OUTPUT PINS 2000 Jan 21 t CSC CSD t DAL t t DCR DAH Figure 8. Interrupt Cycle Timing (68XXX mode OLD DATA Figure 9. Port Timing 37 Product specification SC28L92 DAT SD00149 NEW DATA SD00135 ...
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... Figure 10. Interrupt Timing (80xxx mode) NOTE: RESISTOR REQUIRED FOR TTL INPUT. CLK t CLK t CTC t Rx *NOTE: X2 MUST BE LEFT OPEN SC28L92 X1 2pF 50k to 100k 4pF X2 3.6864MHz Figure 11. Clock Timing 38 Product specification SC28L92 V +0. +0. SD00136 V CC 470 X1 X2* TO UART CIRCUIT SD00695 ...
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... BIT TIME ( CLOCKS) t TXD t TCS Figure 12. Transmitter External Clocks t t RXS RXH Figure 13. Receiver External Clock D2 D3 BREAK D9 START D10 STOP BREAK BREAK Figure 14. Transmitter Timing 39 Product specification SC28L92 SD00138 SD00139 D4 D6 D11 WILL D12 NOT BE WRITTEN TO THE TxFIFO OPR( SD00155 ...
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... BIT 9 BIT MR1( ADD#2 BIT 9 BIT ADD#1 STATUS DATA D0 Figure 16. Wake-Up Mode 40 Product specification SC28L92 D11 D12 D13 D12, D13 WILL BE LOST DUE TO RECEIVER DISABLE. STATUS DATA STATUS DATA D2 D3 D10 RESET BY COMMAND SD00156 BIT 9 ADD#2 1 BIT 9 BIT 9 ...
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... Dual Universal Asynchronous Receiver/Transmitter (DUART 2.4mA INTRN DACKN 125pF I = 2.4mA V return 400 A V return D0–D7 TxDA/B OP0–OP7 125pF Figure 17. Test Conditions on Outputs 2000 Jan 21 +5V for a 0 level CC for a 1 level SS SD00690 41 Product specification SC28L92 ...
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... Philips Semiconductors 3.3V–5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART) PLCC44: plastic leaded chip carrier; 44 leads 2000 Jan 21 42 Product specification SC28L92 SOT187-2 ...
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... Philips Semiconductors 3.3V–5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART) QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 1.75 mm 2000 Jan 21 43 Product specification SC28L92 SOT307-2 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 2000 Jan 21 [1] Copyright Philips Electronics North America Corporation 2000 Document order number: 44 Product specification SC28L92 All rights reserved. Printed in U.S.A. Date of release: 01-00 9397 750 06796 ...